J
John Mark Beardslee
Researcher at Synopsys
Publications - 9
Citations - 853
John Mark Beardslee is an academic researcher from Synopsys. The author has contributed to research in topics: Debugging & Hardware description language. The author has an hindex of 9, co-authored 9 publications receiving 853 citations.
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Patent
Method and user interface for debugging an electronic system
TL;DR: In this paper, techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described, where the hardware designs have been designed in HDL and have been fabricated in integrated circuit products with limited input/output pins.
Patent
Hardware debugging in a hardware description language
TL;DR: In this paper, techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described, where the hardware designs have been designed in HDL and have been fabricated in integrated circuit products with limited input/output pins.
Patent
Method and system for debugging an electronic system
TL;DR: In this paper, the authors present techniques and systems for debugging an electronic system having instrumentation circuitry included therein, which facilitate analysis, diagnosis and debugging fabricated hardware designs at a HDL level.
Patent
Hardware/software co-debugging in a hardware description language
TL;DR: In this article, techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at the hardware description language (HDL) level are described, although the hardware designs were designed in HDL and have been fabricated in integrated circuit products with limited input/output pins.
Patent
Hardware-based HDL code coverage and design analysis
TL;DR: In this paper, techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described, which enable the hardware designs within the integrated circuit products to be analyzed and diagnosed at the HDL level at speed.