Throughout the decades of continuous advances in semiconductor technology, from the discrete devices of the late 1950s to today's billon-transistor system-on-chip, there have always been concerns about the ability of components to operate safely in an increasingly disruptive electromagnetic environment. This paper provides a nonexhaustive review of the research work conducted in the field of electromagnetic compatibility (EMC) at the IC level over the past 40 years. It also brings together a collection of information and trends in IC technology, in order to build a tentative roadmap for the EMC of ICs until the year 2020, with a focus on measurement methods and modeling approaches.

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The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

Typical input and output stages for a digital integrated circuit (IC) have been simulated using the electronic circuit analysis program SPICE2. An unwanted radio-frequency (URF) signal is injected into the circuit at the point where the output stage is connected to an input stage. The effects of varying the magnitude, the frequency, and the relative phase angle of the URF source are studied. An example of a system-level analysis based on the electronics-level simulations is also given.

Predicting URF Upset of MOSFET Digital IC's

A description is given of measurements of RF upset levels on two D-type flip-flops, the CD4013B and 54ALS74A, which are functionally identical but fabricated from different technologies: CMOS and low-power Schottky. Continuous-wave electromagnetic interference (CW EMI) from 1 MHz to 200 MHz was coupled into the clock, data, and collector bias, V/sub cc/, ports of each device type while test vectors were used to verify normal operation and subsequent upsets. Both the CMOS and the Schottky devices show decreasing RF susceptibility with increasing frequencies from 1 to 200 MHz. The differences in the susceptibility levels measured for the two technologies are apparent in the data and clock ports' upset levels. >

RF upset susceptibilities of CMOS and low power Schottky D-type flip-flops

Delays induced by radio frequency interference (RFI) in CMOS inverters are measured under radiated and capacitively coupled interference. Experimental and theoretical investigations of the effects of the RFI coupling mode (capacitive versus inductive) on the amount of induced delay are presented and a worst-case coupling mode is identified. A formula to predict delays caused by in-band low-level RFI in CMOS inverters is introduced. This formula uses experimentally determined parameters which are dependent on the coupling mode. The change in delay is computed as a function of the induced voltage disturbance, which in turn can be computed from the incident field using linear frequency-domain analysis. The formula accounts for the dependence of the induced delay on the phase and amplitude of the RFI signal as well as on the slew rate of the logic transitions. A delay growth phenomenon in a string of inverters is identified and characterized. A correction to the delay prediction formula is proposed in order to take this growth into account in worst-case predictions. >

Prediction of delays induced by in-band RFI in CMOS inverters

The potential of high-power microwave radiation to couple into and generate malfunction in microelectronic systems has become a serious concern; however, the underlying electronic mechanisms are not well understood. We present results of experiments on the response of a typical CMOS integrated circuit to pulsed microwave excitation. Our results show that electrostatic discharge protection devices detect the pulse envelope of the microwave carrier via its nonlinear conductance. The device characteristics are analyzed using device physics to describe the quasi-static and non-quasi-static behavior of the protection circuits and define the regime of operation in terms of excitation frequency. The results of experiments and analysis lead to the development of an improved effects model based on Berkeley Short-channel IGFET Model using a body resistor network. Good agreement between experiments and transient and harmonic-balance simulations is demonstrated. The results show that a deterministic method of evaluating electromagnetic effects using physical, scalable device parameters is feasible.

Study of Basic Effects of HPM Pulses in Digital CMOS Integrated Circuit Inputs

The investigation into the susceptibility of a IK bit memory as described in this paper was undertaken with the intention of gaining understanding of the nature and consequences of electromagnetic interference (EMI) on complex digital devices. The author is involved in the clearance of military aircraft for electromagnetic compatibility and this requires know­ ledge of system response to EMI. To have confidence in the hardness of an aircraft system it is necessary not only to design and build equipment capable of working in the severe electromagnetic environment encountered and created by modern military aircraft but also to be in a position to assess equipment hardness during manufacture and when installed in the aircraft.

John N Roach

Papers

The Susceptibility of a 1K NMOS Memory to Conducted Electromagnetic Interference