John P. Miller

TL;DR: In this paper, a network device receives packets from a first network segment, time stamps the packets as they arrive, and transmits the packets to a second network segment to conserve network bandwidth.

TL;DR: In this paper, an output clock signal that is selectively synchronized to one of two generally free-running input clock signals that may be of the same or different frequency and phase is presented.

TL;DR: In this paper, the first and second circuits are used to produce appropriately synchronized handshake signals to ensure switching occurs between the two input clock signals in a manner whereby the output clock signal does not have any clock pulses that are shrunk or narrowed.

TL;DR: In this article, a clock signal switching device selects an outputted clock signal (CLKA or CLKB) based on a selected signal SEL, but, since the switching timing is controlled by a handshake signal (SELA or SELB) synchronized to each clock signal, the selection is not interrupted in the course of a pulse.

TL;DR: In this article, a state machine bit group is selected from a plurality of bit groups of a digital system for debugging the state machine connected to the selected bit group, using existing output pins of the digital system.