Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Position independent testing of circuits

Disclosed is a semiconductor wafer, and the method of making the same, the wafer being formed to have a multiplicity of raised contact pads on its surface. The contact pads are formed with conductors which are disposed on the surface of the wafer and which are coupled to internal circuitry embedded in the wafer through vias in the wafer's surface. The contact pads are in a raised elevational relationship relative to the surface conductors. After the wafer is fully processed, by dicing individual integrated circuit chips out of the wafer, each chip can then be mounted on a higher level of assembly, such as a printed circuit board. The raised contact pads originally formed on the wafer, and therefore formed on each individual chip, provide the contact points by which the chip can be bonded with matingly arranged contact pads on the higher level of assembly.

Wafer with elevated contact structures

An unsingulated semiconductor wafer is provided. Electrical interconnect elements are formed on the unsingulated wafer such that the interconnect elements are electrically connected to terminals of the semiconductor dice composing the wafer. At least a portion of the interconnect elements extend beyond the boundaries of the dice into the scribe streets separating the individual dice. Thereafter, the wafer is singulated into individual dice.

Fan out of interconnect elements attached to semiconductor wafer

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Scan circuit low power adapter with counter

A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

Digital bus monitor integrated circuits

A monometallic batch process for forming beam leads of a preferred metal such as aluminum or gold. The process is applied to a wafer of finished microelectronic devices already having metal contact pads of the same preferred metal. Where aluminum is the desired metal, high deposition rates are used to minimize aluminum oxide contamination. High yield is achieved by forming the beam leads to have an elevated cantilevered configuration, by deep scribing of the wafer and, when desired, by providing an energy absorbing cushion to reduce the effect of collisions between chip edges and beam leads.

John R. Davis

Papers

Batch process providing beam leads for microelectronic devices having metallized contact pads