An integrating phase detector includes a phase comparator and an integrating load impedance. The phase comparator is a voltage-input, current-output logic gate such as a OR/NOR gate, or a XOR/XNOR gate having first and second inputs for comparing the phase of first and second input signals. The current output of the logic gate provides an output current pulse proportional to the phase difference between the first and second input signals. The integrating load such as a passive resistor-capacitor network is coupled to the current output of the phase detector for directly integrating the current pulse and providing a DC voltage proportional to the phase difference between the first and second input signals. The minimum pulse width of the output current pulse is substantially limited only by the fT of the devices used in the logic gate. The improved bandwidth of the phase detector also increases the linear operating range by increasing the range of phase in which the output current pulse is proportional to the input phase difference.

Integrating phase detector

A phase-locked-loop (PLL) circuit comprising a phase comparator, a current-variable charge pump, a voltage-controlled oscillator, a low-pass filter, and frequency dividers. The charge pump drive current is controlled in steps or continuously depending on the operating mode.

Phase-locked-loop circuit having a charge pump

A Phase Locked Loop (PLL) circuit includes a control signal generator, a digital phase detector, logic gates, a charge pump (charge/discharge circuit), a transmission gate, a loop filter, a lead-lag filter and a voltage controlled oscillator (VCO). Outputs of the digital phase detector are coupled through the logic gates to inputs of the charge pump. An output of the charge pump is coupled to the capacitor and to a first input/output of the transmission gate. A second input/output of the transmission gate is coupled to an input of the loop filter whose output is coupled to an input of the VCO whose output is coupled to a first input of the digital phase detector. A second input of the digital phase detector is coupled to a source of a reference frequency signal. The control signal generator generates non-overlapping complementary control signals with one of same connected to the logic gates and the other connected to the transmission gate. Accordingly, the electrical path from the digital phase detector to the charge pump through the logic gates is closed and the electrical path from the capacitor to the loop filter is open or vice versa. The loop filter includes an operational amplifier with AC feedback which is controlled by the same signal which controls the logic gates. The PLL circuit is typically formed on a single integrated circuit silicon chip using CMOS technology.

Phase locked loop circuit with digital control

A phase locked loop system having a non-linear voltage controlled oscillator (VCO) is provided with a variable gain charge pump The charge pump supplies a pump current to an integrating network which transforms the pump current into a frequency-modulating input voltage The frequency-modulating input voltage is applied to an input of the VCO The frequency-modulating input voltage is also coupled to a gain control input of the variable gain charge pump so that the magnitude of the pump current will be a function of the absolute value of the frequency-modulating voltage A substantially constant loop gain may be obtained in the phase locked loop system by arranging the gain function of the variable gain charge pump in counterposed relation to the slope of a VCO transfer function defining the nonlinear relation between the frequency-modulating input voltage of the VCO and the output frequency of the VCO

Variable frequency system having linear combination of charge pump and voltage controlled oscillator

A Phase Locked Loop (PLL) circuit (100) includes a compensation circuit (120) which corrects for non-linear sensitivity of a varactor of a voltage controlled oscillator (VCO) (104) which is part of the circuit. The varactor is employed as a capacitance tuning element. The compensation circuit controls the sensitivity of a charging/discharging circuit (a charge pump 114) of the PLL circuit with a feedback signal which is derived from an input to the VCO. The sensitivity characteristic of the charge pump is made the complement of the non-linear portion of the VCO sensitivity characteristic.

Compensated phase locked loop circuit

In accordance with the present invention, there is provided a method of substantially flattening the modulation response in a frequency synthesizer. The method includes the steps of generating a synthesized frequency in response to a filtered control signal; scaling the synthesized frequency with a scalar; generating a control signal, having a response substantially the reciprocal of the frequency generation response, and indicative of the phase relationship between a reference frequency and the scaled, synthesized frequency; and filtering the control signal, whereby the interaction of the phase relationship control signal response and the frequency generation response approximates a flat modulation response.

John R. Sonnenberg

Papers

Frequency synthesizer modulation response linearization