A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto.

Multistandard video decoder and decompression system for processing encoded bit streams including a video formatter and methods relating thereto

A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto

Data pipeline system and data encoding method

Methods and systems for capacitive proximity and contact sensing employ one or more simple sensors (which may be a conductive fiber or pattern of conductive ink) in communication with a microcontroller. Digital signal processing executed by the microcontroller enables resolution enhancement, automatic and continuous calibration, noise reduction, pattern recognition and the configuration of virtual sensors capable of detecting how an object incorporating the sensors is being manipulated.

Capacitive sensor systems and methods with increased resolution and automatic calibration

An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Token-based adaptive video processing arrangement

A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

Memory interface for reading/writing data from/to a memory

A time interval data processing circuit uses a pipelined hardware data processor to perform the conversion of incoming time stamp data into time interval results. These results can be further processed into a hardware accumulated histogram or can be compared against limits to determine if a time interval trigger condition has occurred. In the first stage of the pipeline, the processing circuit subtracts the two time stamps from the current and the previous event to determine the time interval between events being measured. The second stage checks the measurement result against minimum and maximum limits and determines which bin the measurement belongs in. The limit testing determines if the measurement fits the histogram limits and also yields the data required to perform measurement triggering on time intervals. The third stage of the pipeline increments the appropriate histogram bin in RAM. The first and third stages of the pipeline are themselves pipelined in substages. To facilitate pipelining in storing the histogram results, the circuit uses dual port RAMs to achieve a fast data accumulation rate. When histogramming, the stored bin data must be incremented each time a new measurement occurs. The third pipeline stage read, increment, write operation is pipelined in substages by adding a latch in the data incrementing loop for the dual port RAM. The latch also provides a way of avoiding access conflicts when the same bin is incremented repeatedly.

Time interval triggering and hardware histogram generation

A method and apparatus for block averaging measurement data from dynamic, repeating input signals, for example, frequency modulated signals, take into account the time variability of the measurement sampling. Each block of measurement data is referenced to a synchronizing stimulus, and measurements are averaged both on the time axis and on the modulation axis. On the time axis, the time alignment for each individual measurement is placed at the center of the time interval during which the measurement was made. For each block of data acquired, the measurement blocks are averaged together in both dimensions, time (x-axis) and modulation (y-axis result being computed), using a stimulus synchronizing signal provided by the user as a time reference (time=0). The stimulus synchronizing signal should be a stable reference with respect to the modulation function being measured. For example, if frequency versus time is being measured, the reference should identify a repeating frequency reference. The times from the stimulus synchronizing reference to the input signal events are measured and accounted for in the block averaging method of the invention.

John S. Schmitz

Papers

Time interval triggering and hardware histogram generation

Block averaging of time varying signal attribute measurements