Swappable Logic Units (SLUs) were introduced by the author previously (1996) to play a role in virtual hardware subsystems that is analogous to the role of pages or segments in virtual memory subsystems. The intention is that a conventional operating system can be extended to manage SLU circuitry implemented using FPGA real estate. In order to minimise operating system overheads, two particular SLU-based virtual hardware models were deemed practical: a "sea of accelerators" model and a "parallel harness" model. This paper looks in some detail at how SLUs will fit within the overall environment of a fairly conventional hardware/software system. First, there is a discussion of the FPGA-based hardware environment for SLUs, followed by a discussion of the software environment from which SLUs might be used. After this, there is a description of the operational properties that SLUs can have, and how these fit in with the two virtual hardware models. Finally, proposals for standard interfaces between SLUs and their environment are discussed. These interfaces can be regarded as constraints on the designers of SLU circuitry or, more positively, as suppliers of an enriched context within which such circuitry operates. The overall impact of the work presented in the paper is to show that it is feasible to incorporate configurable hardware within traditional computer systems that use high-level language programs and computer operating systems. That is, it should not always be necessary to devise special-purpose hardware/software systems to realise custom computing.

The swappable logic unit: a paradigm for virtual hardware

As custom computing machines evolve, it is clear that a major bottleneck is the slow interconnection architecture between the logic and memory. This paper describes the architecture of a custom computing machine that overcomes the interconnection bottleneck by closely integrating a fixed-logic processor, a reconfigurable logic array, and memory into a single chip, called OneChip-98. The OneChip-98 system has a seamless programming model that enables the programmer to easily specify instructions without additional complex instruction decoding hardware. As well, there is a simple scheme for mapping instructions to the corresponding programming bits. To allow the processor and the reconfigurable array to execute concurrently, the programming model utilizes a novel memory-consistency scheme implemented in the hardware. To evaluate the feasibility of the OneChip-98 architecture, a 32-bit MIPS-like processor and several performance enhancement applications were mapped to the Transmogrifier-2 field programmable system. For two typical applications, the 2-dimensional discrete cosine transform and the 64-tap FIR filter, we were capable of achieving a performance speedup of over 30 times that of a stand-alone state-of-the-art processor.

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Memory interfacing and instruction specification for reconfigurable processors

A reconfigurable computing system and method of use are provided for interfacing a plurality of application programs running on a host system to one or more hardware objects defined in one or more configuration files. The system includes reconfigurable computing circuitry comprising flexibly configurable circuitry operable for interfacing and implementing one or more hardware objects with one or more of the application programs. The system further includes memory circuitry associated with the reconfigurable computing circuitry for system information storage, and communications interfaces for connecting the reconfigurable computing circuitry and the memory to the host computer. The flexibly configurable circuitry further comprises one or more FPGAs and one or more programmable logic devices (“PLDs”), SRAM and EEPROM memory, and all the necessary connectors and support circuitry. The reconfigurable computing system and method of the present invention can be implemented on either a PCMCIA platform, a PCI platform, or any other bus structure without changing the basic functionality and claimed functionality of the reconfigurable computing system. Additionally, the reconfigurable computing system and method of this invention are well suited to be implemented in a portable computing environment.

Reconfigurable computing system and method and apparatus employing same

A system (20) is disclosed including reconfigurable logic circuit (40) having programmable logic (50), interface memory (60), and logic design memory (80). Memory (80) stores a number of logic designs each operable to configure programmable logic (50). Also included is computer (22) coupled to reconfigurable logic circuit (40) that concurrently executes one or more application programs and an interface program. The application programs generate a number of requests to utilize reconfigurable logic circuit (40) and the interface program responds to the requests by opening a number of coexisting program interfaces. Reconfigurable logic circuit (40) is responsive to the interface program to provide a number of interface buffers in memory (60) that each belong to a corresponding one of the interfaces and are each operable to store data passing between computer (22) and reconfigurable logic circuit (40).

Reconfigurable logic for a computer

This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a nehvork control algorithm. We developed a new tightly coupled Held Programmable Gate Array (FPGA) and Micro-Processing Unit (MPU) system named. Yet Another Re-Definable System (YARDS). It comprises three programmable devices which equateto high flexibility. These devices are the RISC-type MPU with memories, programmable inter-connection devices, and FPGAs. Using these, this system supports various styles of coupling between the FPGAs and the MPU which are suitable for constructing transport data processing. In this paper, two applications of the systemin the telecommunications field are given. One is an Operation, Administration, and Management (OAM) cell operations on an AsynchronousTransfer Mode (ATM) network. The other is a dynamic configuration protocol enables the updateor changeof the functions of the transport data processing system on-line. This is the first approach applying the FPGA/MPU hybrid system to the telecommunications field.

YARDS: FPGA/MPU hybrid architecture for telecommunication data processing

We define reconfigurable computing systems as those machines that use the reconfigurable aspects of field programmable gate arrays (FPGAs) to implement an algorithm Researchers throughout the world have shown that computationally intensive software algorithms can be transposed directly into hardware design for extreme performance gain Hardware objects are algorithms implemented as dynamically downloadable hardware designs Hardware objects execute on reconfigurable computing systems based on SRAM-style FPGAs A hardware object can be created via schematic and VHSIC hardware description language or Verilog hardware description language To use a hardware design in a software program, it must be converted into a hardware object The hardware object can be used over and over or in combination with other hardware objects This hardware object technology method of programing reconfigurable computers is the subject of this paper© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering Downloading of the abstract is permitted for personal use only

Hardware object programming on the EVC1: a reconfigurable computer

Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing

We define reconfigurable computing systems as those machines that use the reconfigurable aspects of Field Programmable Gate Arrays (FPGA) to implement an algorithm. Researchers throughout the world have shown that computationally intensive software algorithms can be transposed directly into hardware design for extreme performance gain [1,2,3]. Hardware objects are algorithms implemented as dynamically downloadable hardware designs. Hardware objects execute on reconfigurable computing systems based on SRAM-style Field Programmable Gate Arrays (FPGA). A Hardware Object can be created via schematic and VHSIC Hardware Description Language (VHDL) or Verilog hardware description language. To use a hardware design in a software program, it must be converted into a Hardware Object. The Hardware Object can be used over and over or in combination with other Hardware Objects. This H.O.T. (Hardware Object Technology)ℳ method of programming reconfigurable computers is the subject of this paper [4].

Creation of Hardware Objects in a Reconfigurable Computer

Success in the marketplace may well depend upon the ability to upgrade and test hardware designs instantly around the world. An upgrade management strategy requires more than just the bitstream file, email or a JTAG cable. A well-managed methodology, capable of transmitting bitstreams directly into targeted FPGAs over the network or internet is an essential element for a successful FPGA based product strategy. Virtual Computer Corporation’s HOTMan, Bitstream Management Environment combines a feature rich cross-platform API with an Object Oriented Bitstream technique for Remote Upgrading of Hardware over the Internet.

Net-aware bitstreams that upgrade FPGA hardware remotely over the Internet: creating intelligent bitstreams that know where to go, what to do when they get there, and can report back when they're done

Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional description of the circuit, with no timing consideration. On the other hand, simulation runs mainly on subsets of the entire input domain. Furthermore, these tools provide results in a format (e.g. state graphs, bit vectors or signal waves) that remain disconnected from the real output of the application. We introduce in this paper the process of validation applied to digital designs in FPGAs. It allows the designer the ability to test his/her implementation using the real data of the application and providing real results. With such real data, it becomes easier to identify where the error occurs and then to understand it.

John Schewel

Papers

Hardware object programming on the EVC1: a reconfigurable computer

Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing

Creation of Hardware Objects in a Reconfigurable Computer

Net-aware bitstreams that upgrade FPGA hardware remotely over the Internet: creating intelligent bitstreams that know where to go, what to do when they get there, and can report back when they're done

IP validation for FPGAs using Hardware Object Technology(tm)