Preface. About the Authors. Acknowledgments. 1 Power Amplifier Fundamentals. 1.1 Introduction. 1.2 Definition of Power Amplifier Parameters. 1.3 Distortion Parameters. 1.4 Power Match Condition. 1.5 Class of Operation. 1.6 Overview of Semiconductors for PAs. 1.7 Devices for PA. 1.8 Appendix: Demonstration of Useful Relationships. 1.9 References. 2 Power Amplifier Design. 2.1 Introduction. 2.2 Design Flow. 2.3 Simplified Approaches. 2.4 The Tuned Load Amplifier. 2.5 Sample Design of a Tuned Load PA. 2.6 References. 3 Nonlinear Analysis for Power Amplifiers. 3.1 Introduction. 3.2 Linear vs. Nonlinear Circuits. 3.3 Time Domain Integration. 3.4 Example. 3.5 Solution by Series Expansion. 3.6 The Volterra Series. 3.7 The Fourier Series. 3.8 The Harmonic Balance. 3.9 Envelope Analysis. 3.10 Spectral Balance. 3.11 Large Signal Stability Issue. 3.12 References. 4 Load Pull. 4.1 Introduction. 4.2 Passive Source/Load Pull Measurement Systems. 4.3 Active Source/Load Pull Measurement Systems. 4.4 Measurement Test-sets. 4.5 Advanced Load Pull Measurements. 4.6 Source/Load Pull Characterization. 4.7 Determination of Optimum Load Condition. 4.8 Appendix: Construction of Simplified Load Pull Contours through Linear Simulations. 4.9 References. 5 High Efficiency PA Design Theory. 5.1 Introduction. 5.2 Power Balance in a PA. 5.3 Ideal Approaches. 5.4 High Frequency Harmonic Tuning Approaches. 5.5 High Frequency Third Harmonic Tuned (Class F). 5.6 High Frequency Second Harmonic Tuned. 5.7 High Frequency Second and Third Harmonic Tuned. 5.8 Design by Harmonic Tuning. 5.9 Final Remarks. 5.10 References. 6 Switched Amplifiers. 6.1 Introduction. 6.2 The Ideal Class E Amplifier. 6.3 Class E Behavioural Analysis. 6.4 Low Frequency Class E Amplifier Design. 6.5 Class E Amplifier Design with 50# Duty-cycle. 6.6 Examples of High Frequency Class E Amplifiers. 6.7 Class E vs. Harmonic Tuned. 6.8 Class E Final Remarks. 6.9 Appendix: Demonstration of Useful Relationships. 6.10 References. 7 High Frequency Class F Power Amplifiers. 7.1 Introduction. 7.2 Class F Description Based on Voltage Wave-shaping. 7.3 High Frequency Class F Amplifiers. 7.4 Bias Level Selection. 7.5 Class F Output Matching Network Design. 7.6 Class F Design Examples. 7.7 References. 8 High Frequency Harmonic Tuned Power Amplifiers. 8.1 Introduction. 8.2 Theory of Harmonic Tuned PA Design. 8.3 Input Device Nonlinear Phenomena: Theoretical Analysis. 8.4 Input Device Nonlinear Phenomena: Experimental Results. 8.5 Output Device Nonlinear Phenomena. 8.6 Design of a Second HT Power Amplifier. 8.7 Design of a Second and Third HT Power Amplifier. 8.8 Example of 2nd HT GaN PA. 8.9 Final Remarks. 8.10 References. 9 High Linearity in Efficient Power Amplifiers. 9.1 Introduction. 9.2 Systems Classification. 9.3 Linearity Issue. 9.4 Bias Point Influence on IMD. 9.5 Harmonic Loading Effects on IMD. 9.6 Appendix: Volterra Analysis Example. 9.7 References. 10 Power Combining. 10.1 Introduction. 10.2 Device Scaling Properties. 10.3 Power Budget. 10.4 Power Combiner Classification. 10.5 The T-junction Power Divider. 10.6 Wilkinson Combiner. 10.7 The Quadrature (90 ) Hybrid. 10.8 The 180 Hybrid (Ring Coupler or Rat-race). 10.9 Bus-bar Combiner. 10.10 Other Planar Combiners. 10.11 Corporate Combiners. 10.12 Resonating Planar Combiners. 10.13 Graceful Degradation. 10.14 Matching Properties of Combined PAs. 10.15 Unbalance Issue in Hybrid Combiners. 10.16 Appendix: Basic Properties of Three-port Networks. 10.17 References. 11 The Doherty Power Amplifier. 11.1 Introduction. 11.2 Doherty's Idea. 11.3 The Classical Doherty Configuration. 11.4 The 'AB-C' Doherty Amplifier Analysis. 11.5 Power Splitter Sizing. 11.6 Evaluation of the Gain in a Doherty Amplifier. 11.7 Design Example. 11.8 Advanced Solutions. 11.9 References. Index.

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High Efficiency RF and Microwave Solid State Power Amplifiers

In modern wireless communication systems, it is very important to realize simultaneously high-efficiency and linear operation of power amplifiers. This paper-overview describes the historical aspect of the Doherty approach to the power-amplifier design introduced in 1936 and modern trends in Doherty amplifier (DA) design techniques using multistage and asymmetric multiway architectures. To increase efficiency over the power backoff range, the switchmode class-E, conventional class-F, or inverse class-F operation mode by controlling the second and third harmonics can be used in the load network. The DA with a series-connected load, and inverted, push–pull, balanced, and parallel Doherty architectures are also described and discussed. Finally, examples of the lumped DA implemented in monolithic microwave integrated circuits, digitally driven Doherty technique, and broadband capability of the two-stage DA are given.

High-Efficiency Doherty Power Amplifiers: Historical Aspect and Modern Trends

The aim of this paper is to present a closed-form formulation suitable for a direct computer-aided design synthesis of a Doherty amplifier employing a Class F design strategy for the Main (or Carrier) device. For this purpose, starting from a simplified model for the adopted active devices, the behavioral analysis of the Class F Doherty amplifier is carried out as a function of the input signal. A particular emphasis is dedicated to put into evidence the differences existing when a simple tuned load harmonic termination is considered. The theoretical aspects are deeply discussed and an experimental validation is also provided.

Theory and Experimental Results of a Class F AB-C Doherty Power Amplifier

In this paper, we present a design method for a compact inverted Doherty power amplifier (IDPA), which has high-efficiency and high-power characteristics. An optimum load matching network and an additional offset line, after the matching network of the carrier amplifier, dynamically modulate the load impedance according to the input power drive, while the conventional Doherty power amplifier uses a quarter-wave line to do it. The operational principles and design guide are provided. For experimental verification, a 50-W Doherty amplifier was designed for the pi/4 differential quadrature phase-shift keying application at the 860-MHz band. The measured performance of the IDPA was compared with that of the balanced class-AB amplifier with the same output matching network. At an output power of 50 W, the IDPA performs with 3.16 dB better adjacent channel power ratio (-28 versus -24.84 dBc) and 6.15% higher power-added efficiency (59.02 versus 52.87%) than the class-AB amplifier does.

Design of a High-Efficiency and High-Power Inverted Doherty Amplifier

In part I, the complete theoretical (and nonlinear) analysis of a Doherty amplifier employing a Class AB bias condition for the Main Amplifier and a Class C one for the Auxiliary device has been presented. In this article, the experimental validation of the proposed theory is presented, describing the step-by-step procedure to be adopted when designing an AB-C Doherty. The amplifier was realized at 2.14 GHz in hybrid form using two (0.5 μm, 1 mm gate periphery) GaN HEMTs. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.

The AB-C Doherty power amplifier. Part II: Validation

A new topology of Doherty amplifier is proposed to reduce the circuit size by eliminating the bulky 3 dB 90/spl deg/ hybrid coupler. Unlike the classical Doherty amplifier, the carrier and peak amplifiers are connected in series together with an impedance-inverting network connecting the outputs of both amplifiers. A simple matching circuit between the peak and carrier amplifier replaces the input hybrid coupler. In this way, the need for an input hybrid coupler is eliminated, facilitating integration and miniaturization. The fabricated 2.45 GHz amplifier module using the proposed topology demonstrates enhanced efficiencies in the low- to mid-power ranges and shows good gain flatness. This approach is promising for highly-integrated Doherty-type amplifiers for handset applications.

Joomin Jung

Papers

A new "series-type" Doherty amplifier for miniaturization