An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface of a substrate and a graded pinned surface layer, self-aligned to a gate stack is provided. These photodiodes exhibit reduced image lag, transfer gate leakage, and photodiode dark current generation.

Pinned photodiode structure and method of formation

A semiconductor device includes a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side. The field stop zone includes a first dopant implant and a second dopant implant. The first dopant implant has a first dopant concentration maximum and the second dopant implant has a second dopant concentration maximum with the first dopant concentration maximum being less than the second dopant concentration maximum, and being located closer to the second side than the second dopant concentration maximum.

Semiconductor device with a field stop zone

An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.

High performance cmos devices and methods for making same

PROBLEM TO BE SOLVED: To provide a semiconductor device with the electric field imposed on its gate insulating film relaxed so as to reduce the leakage current, and to enhance the drive current. SOLUTION: The semiconductor device is equipped with gate insulating films 2 and 3 formed in an element forming region on a semiconductor substrate 1, a gate electrode 4 formed through the intermediary of the gate insulating films 2 and 3, and source layers 6a and 6b and drain layers 7a and 7b, which are formed in element forming regions located on both the sides of the gate electrode 4. The gate insulating films 2 and 3 are formed of at least two layers so as to become gradually high in permittivity in a direction from the drain layers 7a and 7b along the source layers 6a and 6b, so that electric field applied to the gate insulating films 2 and 3 is relaxed to so as to reduce the leakage current. COPYRIGHT: (C)2006,JPO&NCIPI

Semiconductor device and method of manufacturing the same

A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.

Method for fabricating a CMOS device

A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.

Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices

Procede de fabrication de dispositifs MOS comportant des regions de la source et du drain a transition progressive. Les regions de la source et du drain sont legerement dopees par implantation d'ions, puis soumises a un cyclage thermique ayant pour objet de diffuser les impuretes implantees. Les regions de la source et du drain sont ensuite fortement dopees pour former des regions de la source et du drain comportant une sous-region fortement dopee et une sous-region faiblement dopee. Les dispositifs realises au moyen de ce procede, auxquels il est possible de donner des dimensions inferieures a un demi-micron, ne sont pas sujets a une charge de l'oxyde de grille et se caracterisent par des tensions de "snapback" elevees.

Joseph E. Farb

Papers

Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices

A latch up free, high voltage, cmos process for sub-half-micron devices