In this work the most recent advances in digital image processing techniques has been used to make vehicle drivers face analysis by detecting symptoms of tiredness and distraction in order to prevent sudden risk situations. The results of the experiments show that a large number of car or trucks accidents can be avoided by detecting real-time physical and psychological states of the drivers in normal driving conditions. There are three main objectives in this design: To detect the driver eyelid movements, to detect the number of frames the driver has his eyes closed and to detect when the driver turns right or left (or bows) his head for a long time. Thus, several well known algorithms have been used and optimized for this field of application, such as spatial and temporal filtering, motion detection, optical flow analysis, etc. Digital signal and image processing techniques have been used together. Furthermore, a low-cost real-time solution based upon FPGA (ALTERA FLEX 10K30, field programmable gate array) has been achieved. Moreover, all the laboratory experiments are being carried out on real automobiles and a very low-cost, low-power and real-time solution based on ALTERA Cyclone Device (EP1C3) is available in the short-term.

http://ieeexplore.ieee.org/iel5/9011/28611/01280262.pdf

A low-cost real-time FPGA solution for driver drowsiness detection

The architecture and design of MVIP-2, a flexible and efficient proposal for implementing an H.263 video coder, is explained in this paper. The MVIP-2 architecture consists of a set of specialized processors for the main tasks (transforms, quantizers, motion estimation and motion compensation) and a RISC processor for the scheduling tasks. The MVIP-2 design has been written in synthesizable hardware description language (HDL) and fully tested with hardware-software co-simulation using standard video sequences. Finally, MVIP-2 has been prototyped onto a system based on an FPGA and a RISC.

An FPGA implementation of a flexible architecture for H.263 video coding

The present invention relates to processing hardware suitable for enabling an integrated chip (5) solution for decoding and/or encoding video data in accordance with a variety of video encoding formats, comprising a pipeline controller (55, 215) and a plurality of processing stages (15-30, 200-210) arranged in a pipeline for processing successive blocks of data corresponding to successive blocks of an image being processed, at least one of said processing stages (15-30, 200-210) being arranged to process a block of data with reference to data from a previously processed image, data arriving at each processing stage at regular intervals, where it is modified and passed on to the next stage, and so on. The pipeline controller (55, 215) may be arranged to specify one of a number of different encoding protocols supported by the pipeline processor, at least one of said processing stages (15-30, 200-210) being arranged to configure itself differently for compatibility with the specified protocol.

Apparatus and method for processing video data

A novel MPEG-2 video processing model, termed Block-Level-Pipeline (BLP) processing scheme, is introduced. Under BLP control, not only does each processing unit process video data on a block-by-block basis in a video decoder, but also accesses external frame memory for motion compensation on a block-by-block basis. Thus, the data bus width requirement and the associated internal buffer sizes can be minimized because the BLP processing model can evenly distribute data bus traffic in time. Besides providing the compact design of data bus and internal buffers, the BLP scheme also can simplify the architecture design of each processing unit because their computation load can be relieved on this block-by-block basis. The description of the BLP design methodology is complete and precise because it takes processing model, resource management, and process management into account. This methodology can provide valuable estimations for system requirements in the early design stages of MPEG-2 products. 
An efficient interlacing frame memory storage organization and a deterministic fairness-priority bus scheduling scheme are also presented. This simple storing pattern can efficiently lower the probability of occurrence of page-break when accessing the external frame memory. Reducing DRAM access latencies is an important issue in a limited bandwidth system design. Unlike other real-time systems, the bus scheduler can be simplified to a deterministic and fairness-priority approach due to only one block of data being conveyed on the bus at one time. With this short-duration data transfer approach, a complicated bus scheduler to prevent starvation conditions is not needed. 
Based on these work, two designs of MPEG-2 video decoders for DVD and HDTV applications are demonstrated collectively in this dissertation.

Processing and storage models for mpeg-2 main level and high level video decoding: a block-level pipeline approach

In this paper a very flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors for the transforms (DCT and IDCT), quantizers (DQ and IQ), motion estimation and motion compensation (ME/MC). The architecture also includes preprocessing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 bit-stream generation. The architecture has been written in synthesizable Verilog and tested using standard video sequences. It has also been prototyped into a development system based on an FPGA and a RISC.

A flexible architecture for H.263 video coding

A high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 ?m dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in real time, the Loop of an MPEG-2 coder for main profile/main level (MP@ML) resolution when running at 40 MHz. MViP is made up of several specific-purpose units (SPUs), an RISC core processor, banks of internal memory and an optimized crossbar network which lets these pipelined SPUs and RISC core work in parallel at a macroblock-level-pipeline, greatly increasing silicon efficiency.

Juan M. Meneses

Papers

A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding