Showing papers by "Juergen Becker published in 2015"

A Distributed Simulation Platform using HLA for Complex Embedded Systems Design

Abstract: Design complex embedded systems demands method and tools that allow the simulation and verification in an efficient and practical way. This paper proposes the development and evaluation of a distributed simulation platform of heterogeneous simulators based on High Level Architecture (HLA), a middleware for distributed discrete event simulation, in order to create an environment with high-performance execution of large-scale, heterogeneous and complex embedded systems. However, integrate hybrid systems is not trivial, because there is no guarantee that two systems that perfectly work separately will work well together. Experimental results of five different scenarios are presented, which integrate five different simulations tools: Ptolemy II, SystemC, Omnet++, Veins, Stage (a Robot Operating System compatible simulator) and physical robots. The experiments show success in application of Wireless Sensor Networks (WSN), power estimation of circuit design, robotic simulation and co-simulation of real robots.

Parallelization of genetic algorithms for sorting permutations by reversals over biological data

Abstract: Reversals are operations of great biological significance for the analysis of the evolutionary distance between organisms. Genome rearrangement through reversals, consists in finding the shortest sequence of reversals to transform one genome represented as a signed or unsigned permutation into another. When genes are non oriented and correspondingly permutations are unsigned, sorting by reversals came arise as a challenging problem in combinatorics of permutations. In fact, this problem is known to be NP-hard, but the question whether it is NP-complete remains open for more than twenty years. When permutations are signed and correspondingly genes are oriented, the problem is known to be in P. A parallelization of a standard GA Genetic Algorithm is proposed for the problem of sorting unsigned permutations. This GA was previously reported in the literature as the most competitive regarding precision for which as control mechanism an 1.5-approximation algorithm was used. For the parallelization, the MPI Library of the C language was used and experiments were performed for calculating the execution time and precision. By increasing the number of individuals, experiment showed improvement in relation to previous approaches. Additionally, a virtualization of the GA using a MicroBlaze processor from Xilinx was performed on OVP for which the average number of executed instructions was of approximately 1.40 Giga instruction per second. In this extended version of this works originally presented in NaBIC 2013 biological data was generated and it was shown how the parallelization can be applied for their analysis. Specifically, the evolutionary distances between different pairs of organism were computed based on the set of non common genes in their mitochondrial DNA genome and the reversal distance between the sequences of common genes.

Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures

Abstract: NoC-based many-core architectures are becoming more and more mainstream. To use such platforms efficiently, it is crucial to map applications onto these architectures while considering the communication demands and the actual load of the NoC architecture. Therefore, this paper proposes a concept for a hardware-based mapping mechanism for applications onto NoC-based architectures. We propose an entire flow from the application graph to the hardware module. We give a notion of: (a) task graph pre-processing, (b) the serialization of the task graph, (c) a protocol for the mapping and (d) dedicated hardware modules inside the routers. In addition, we show potentials of our proposed distributed hardware mapping approach.

Embedded Virtualization Approaches for Ensuring Safety and Security within E/E Automotive Systems

Abstract: Automotive E/E systems are subject to several conflicting non-functional requirements. Monetary costs, shorter technology and time-to-market cycles and rising restrictions to energy consumption build a subset of them. Furthermore, existing safety and security criteria must be met. Because of future game changers, like highly automated driving or share-economy scenarios, the relevance to incorporate such non-functional requirements within the product development will increase. Within the ARAMiS (Automotive, Railway and Avionic Multicore Systems) project funded by BMBF, different use-cases of the industry and scientific partners were analyzed. The project goal is to enable multicore systems across mobility domains and show different technical concept implementations and detail the achieved improvements over traditional systems. In ARAMiS, a special focus is placed on embedded virtualization technologies for ensuring safety and security according to existing standards (ISO26262). For isolation purposes and flexible software relocation of Enterprise Systems, hypervisors are already an attractive and proven approach. Here, we analyze virtualization methods within real-time systems for hardware and software to enable embedded hypervisors for automotive needs. Within this paper, we present results arising from the work in the automotive domain within the ARAMiS research project. For that purpose, we have developed OEM specific demonstrator platforms for evaluation purposes to reflect typical automotive use-cases. These platforms are implemented on different hardware controllers, performance classes and mission scenarios. Specifically, we analyze the operation of mixed integrity systems. As a result, the commonalities and technical challenges between demonstrator platforms are identified, and the suitability of virtualization technologies for embedded multicore controllers for automotive E/E systems is discussed. The results enable next generation scenarios for industry partners and provide guidance for future research activities.

A V2X message evaluation methodology and cross-domain modelling of safety applications in V2X-enabled E/E-architectures

Abstract: The introduction of Vehicular Ad-Hoc Networks (VANETs) enables great potential for improving road traffic flow and especially active safety applications such as cooperative adaptive cruise control (CACC). Such applications not only rely on continuous broadcast of vehicle state information (beacons) of all vehicles, but also have strict real-time requirements. Regarding automotive E/E architectures this continuous broadcasting adds heavy internal E/E data traffic that needs to be processed in real-time by Electronic Control Units (ECUs). In this work we address this issue by proposing a novel cluster-based message evaluation methodology to significantly reduce internal E/E network traffic by discarding irrelevant messages. The approach is only depending on information received over beacons. It combines a vehicle clustering strategy as well as network and vehicle state monitoring capabilities in order to correctly evaluate messages under real-time constraints. The proposed methodology is modeled inside an abstract ECU. It is evaluated by simulating a model-based CACC application under different traffic scenarios. It is shown that a significant reduction of messages is achievable, while still guaranteeing accident-free behavior of CACC.

On-demand reconfiguration for coprocessors in mixed criticality multicore systems

Abstract: Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions In a previous work, we proposed a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems The basic idea how to handle the partial reconfiguration transparently for noncritical tasks, while providing full control and a predictable behavior for safety relevant tasks was described In this paper, we focus on the on-demand partial reconfiguration of coprocessors and its implementation details Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express, taking advantage of the Single-Root I/O Virtualization capabilities in modern PCI Express implementations Experimental results show that compared to the reference software implementation, our concept achieves significantly shorter reconfiguration time with lower variance under various system load situations

Adapting Commercial Off-The-Shelf Multicore Processors for Safety-Related Automotive Systems Using Online Monitoring

Abstract: Multicores, being the latest state-of-the-art technology, gain more and more importance in automotive and aerospace systems. This technology will not only be used in infotainment and non-safety-critical applications but will also be introduced in upcoming safety-critical systems. At the moment, various commercial off-the-shelf processors are available that are, however, not built for such applications. In order to ensure correct system behavior, online monitoring can be used for processors targeting infotainment or general purpose applications. The cores and other bus masters within the MPSoC compete for the exclusive use of shared resources like a memory controller. It is of high importance to provide guarantees of usage in such cases, e.g. in terms of access time and rates. For this purpose we present an online monitoring based on a commercial off-the-shelf multicore processor that provides knowledge about the usage of the direct memory access (DMA) controller in terms of accesses and activation sources. Furthermore, with this information, conclusions about the memory controller workload are drawn. The concept is implemented by using Freescale’s i.MX6 Quad platform, which is targeting automotive infotainment. This paper aims to show how such general purpose multicore processors can be partly adapted to provide evidence for safety related systems.

Power Estimation of an ECDSA Core applied in V2X Scenarios using Heterogeneous Distributed Simulation

Abstract: Embedded systems are steadily growing in complexity and nowadays power consumption additionally plays an important role. Designing and exploring such systems embedded in its environment demand for holistic and efficient simulations. In this work we use a simulation framework based on the HLA (High-Level Architecture) and the modeling tool Ptolemy II to enable complex heterogeneous distributed simulations of embedded systems. In this context, we introduce a co-simulation based power estimation approach by integrating domain-specific simulators as well as off-the-shelf HDL simulator and synthesis tools. This enables cross-domain interaction and generation of realistic on-the-fly stimuli data for Register Transfer Level and Gate Level models as well as the gathering of power estimation data. We apply the framework to a Vehicle-2-X scenario evaluating an ECDSA signature processing core which ensures trustworthiness in vehicular wireless networks. To evaluate dynamic power reduction possibilities on application level we additionally introduce a V2X Message Evaluation technique to reduce signature verification efforts. It shows how realistic on-the-fly stimuli data obtained by the framework can improve the exploration and estimation of dynamic power consumption.