The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two N-word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 /spl mu/m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors.

New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy

To secure a mobile ad hoc network (MANET) in adversarial environments, a particularly challenging problem is how to feasibly detect and defend possible attacks on routing protocols, particularly internal attacks, such as a Byzantine attack. In this paper, we propose a novel algorithm that detects internal attacks by using both message and route redundancy during route discovery. The route-discovery messages are protected by pairwise secret keys between a source and destination and some intermediate nodes along a route established by using public key cryptographic mechanisms. We also propose an optimal routing algorithm with routing metric combining both requirements on a node's trustworthiness and performance. A node builds up the trustworthiness on its neighboring nodes based on its observations on the behaviors of the neighbor nodes. Both of the proposed algorithms can be integrated into existing routing protocols for MANETs, such as ad hoc on-demand distance vector routing (AODV) and dynamic source routing (DSR). As an example, we present such an integrated protocol called secure routing against collusion (SRAC), in which a node makes a routing decision based on its trust of its neighboring nodes and the performance provided by them. The simulation results have demonstrated the significant advantages of the proposed attack detection and routing algorithm over some known protocols.

A Secure Routing Protocol Against Byzantine Attacks for MANETs in Adversarial Environments

Here we demonstrate a magnetic resonance coupling based wireless triboelectric nanogenerator (TENG) and fully self-powered wireless sensors. By integrating a microswitch and an inductor with the TENG, the pulsed voltage output is converted into a sinusoidal voltage signal with a fixed frequency. This can be transmitted wirelessly from the transmit coil to the resonant-coupled receiver coil with an efficiency of 73% for a 5 cm distance between the two coils (10 cm diameter). Analytic models of the oscillating and coupled voltage signals for the wireless energy transfer are developed, showing excellent agreement with the experimental results. A TENG of 40 × 50 mm2 can wirelessly light up 70 LEDs or charge up a 15 μF capacitor to 12.5 V in ~90 s. The system is further utilized for two types of fully self-powered wireless chipless sensors with no microelectronic components. The technologies demonstrate an innovative strategy for a wireless ‘green’ power source and sensing. Renewable energy based wireless power transfer is challenging. Here the authors show a resonant-coupled triboelectric nanogenerator as a wireless power source and have further utilized this system to explore two fully self-powered wireless chipless sensors.

/pdf/conjunction-of-triboelectric-nanogenerator-with-induction-1qbeq242i5.pdf

Conjunction of triboelectric nanogenerator with induction coils as wireless power sources and self-powered wireless sensors.

This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (Field Programmable Gate Array). Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular exponentiation operation required for RSA encryption and decryption. Speed and area comparisons are performed on the optimised designs. The issues of targeting a design specifically for a reconfigurable device are considered, taking into account the underlying architecture imposed by the target technology.

/pdf/efficient-architectures-for-implementing-montgomery-modular-dg97u8x64t.pdf

Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

Network based intrusion detection system is a computer network security tool. In this paper, we present an intrusion detection system based on Self-Organizing Maps (SOM) and Resilient Propagation Neural Network (RPROP) for visualizing and classifying intrusion and normal patterns. We introduce a cluster matching equation for finding principal associated components in component planes. We apply data from The Third International Knowledge Discovery and Data Mining Tools Competition (KDD cup’99) for training and testing our prototype. From our experimental results with different network data, our scheme archives more than 90 percent detection rate, and less than 5 percent false alarm rate in one SYN flooding and two port scanning attack types.

https://www.koreascience.or.kr:443/article/CFKO200211921314913.pdf

Hybrid Neural Networks for Intrusion Detection System

In this paper, two implementation methods to optimize a 1024-bit RSA processor are presented. The Montgomery algorithm is used and modified considering large bit modular multiplication. We propose two architectures for 1024-bit RSA processing in order to reduce the required hardware resources and to achieve speed improvement. One reduces the hardware resources using the L-R (left to right) binary method, and the other achieves speed improvement using the R-L (right to left) binary method. We have implemented two single-chip 1024-bit RSA processors based on the proposed architectures in 0.5-/spl mu/m SOG technology using Verilog-HDL. As a result, it is shown that each architecture contributes to speed improvement and area saving.

Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm

Wireless power transfer analysis of circular and spherical coils under misalignment conditions for biomedical implants.

In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding.

A 2048 complex point FFT architecture for digital audio broadcasting system

In this paper, two optimum implementation schemes are proposed in soft output Viterbi algorithm (SOVA) with high performance. One is modifying the architecture known as two-step SOVA scheme in order to obtain high speed. The other is lowering the reliability values to a same level with a scaling factor 0.25 or 0.33 for hardware implementation in order to compensate for the distortion. Also, we have implemented one step SOVA and the modified architecture for comparison of two schemes with 0.65 /spl mu/m Samsung SOG technology using Verilog HDL. At result, The modified architecture provides higher SNR performance by 2 dB at the BER 1E-04 than that of the general SOVA. Also we have obtained good performance by using a fixed scaling factor, by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to high performance.

A modified two-step SOVA-based turbo decoder with a fixed scaling factor

In this paper, we evaluate the hardware implementation method of general DCT/IDCT compatible architecture with minimum resource and high speed. We proposed and implemented the hardwired DA (distributed arithmetic) method with radix-2 multibit coding for the minimum resource, and we used symmetric transpose memory for high speed. Generally, IDCT procedure consists of two ID-IDCT procedures and one transpose. This architecture shows some resources of IDCT core are reusable for DCT process. We propose a general scheme for the processing element of which the gate count is 8.6 K for DCT and 9.2 K for IDCT, through Verilog HDL simulation in 0.65 um SOG technology. Also, we verify that the simulation results using Matlab are acceptable for IEEE Std 1180-1990.

Jun Rim Choi

Papers

Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm

Wireless power transfer analysis of circular and spherical coils under misalignment conditions for biomedical implants.

A 2048 complex point FFT architecture for digital audio broadcasting system

A modified two-step SOVA-based turbo decoder with a fixed scaling factor

A compatible DCT/IDCT architecture using hardwired distributed arithmetic