Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energy-efficient systems. However, this technology is limited with regard to speed, power, VDDmin, and yield due to process variation in transistors and memrisitive devices as well as the issue of read disturbance. This paper examines trends in the design of device and circuits for on-chip nonvolatile memory using memristive devices as well as the challenges faced by researchers in its further development. Several silicon-verified examples of circuitry are reviewed in this paper, including those aimed at high-speed, area-efficient, and low-voltage applications.

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

High linearity CMOS radio receivers often exploit linear V-I conversion at RF, followed by passive down-mixing and an OpAmp-based Transimpedance Amplifier at baseband. Due to nonlinearity and finite gain in the OpAmp, virtual ground is imperfect, inducing distortion currents. This paper proposes a negative conductance concept to cancel such distortion currents. Through a simple intuitive analysis, the basic operation of the technique is explained. By mathematical analysis the optimum negative conductance value is derived and related to feedback theory. In- and out-of-band linearity, stability and Noise Figure are also analyzed. The technique is applied to linearize an RF receiver, and a prototype is implemented in 65 nm technology. Measurement results show an increase of in-band IIP 3 from 9 dBm to >20 dBm, and IIP2 from 51 to 61 dBm, at the cost of increasing the noise figure from 6 to 7.5 dB and <;10% power penalty. In 1 MHz bandwidth, a Spurious-Free Dynamic Range of 85 dB is achieved at <;27 mA up to 2 GHz for 1.2 V supply voltage.

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Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity

The requirements of next-generation wireless terminals are driving RFIC design toward ubiquitous multistandard connectivity at reduced power consumption and cost [1–3]. While the use of scaled CMOS technology is required to allow economically feasible single-chip integration with a digital processor, a Software-Defined Radio (SDR) is the preferred approach to provide a reconfigurable platform, that covers a broad range of noise/linearity specifications while offering the best power/performance trade-off [4,5].

A 2mm 2 0.1-to-5GHz SDR receiver in 45nm digital CMOS

This paper describes a fully integrated 130 nm CMOS 2×2 MIMO tri-band dual-mode transceiver for fixed and mobile WiMAX and IEEE 802.11a/b/g/n applications. The proposed transceiver features reduced RF interface (only 4 RF pins) with the wideband circuit topology of the LNA and drive amplifier that minimizes the performance degradation. With carefully chosen LO frequency planning, the transceiver is capable of operating at 2.3-2.7 GHz, 3.3-3.9 GHz, and as well as 5.1-5.9 GHz bands covering whole frequency spectrum of fixed and mobile WiMAX and WLAN. The measured noise figure of the receiver is 3.6-4.2, 4.2-4.7, and 5.4-6.2 dB for each 2/3/5 GHz bands respectively. The measured PLL phase noise from 1 kHz to 10 MHz is 0.5/0.8/0.95 rms degree for 2/3/5 GHz bands respectively. The transceiver ensures low EVM over the wide dynamic range due to linear RX and TX signal paths and low integrated PLL phase noise characteristics.

A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications

This paper presents a fully integrated 2 RX × 1 TX dual-band direct-conversion mobile WiMAX transceiver in a 65 nm CMOS technology. The frequency division ratios of 4 for the low band (2.3-2.7 GHz) and 8/3 for the high band (3.3-3.8 GHz) are employed to provide high immunity to the VCO pulling and to cover the entire frequency range with a single VCO. A "distribute-then-fractional" frequency plan is proposed to provide the frequency division ratios without degrading the LO signal integrity in the LO distribution path. The proposed plan is achieved by an inductor-less LO distribution with a novel compact dual-mode fractional divider. A noise-shaping transimpedance amplifier (TIA) is also proposed to mitigate the flicker noise of scaled CMOS devices. The two receivers consume 214.1 mW and 247.7 mW in the low-band and the high-band operations, which are lower than the power consumption of the mobile WiMAX transceivers reported previously. In spite of the low power consumption, the receivers achieve the total noise figure of 3.8 dB and 4.5 dB in the low-band and the high-band operations by virtue of the proposed noise-shaping TIA.

A Fully Integrated 2 $\times$ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS

High-bandwidth (BW) and large-capacity storage systems with NAND Flash memory (hereinafter referred to as “NAND”) have been increasingly required for big data applications, such as the field of advanced biomedical science [1]. However, a conventional NAND interface (I/F), e.g., Toggle DDR, with multi-drop bus topology has a tradeoff between BW and capacity due to the large load capacitance of NAND packages (PKGs). Although increasing the number of parallelized lanes of Toggle DDR improves both BW and capacity, it costs a large number of pins/wires on a controller/PCB. In order to overcome these problems, a daisy-chained serial I/F has been proposed [2]. In the I/F, bridge chips mask large load capacitance of NAND PKGs seen from a controller’s transmitter (TX) so that a 12.8Gb/s downlink is realized. However, the multi-band multiplexing technique employed in [2] has a drawback in the difficulty in implementing an uplink because severe timing control is required for cumulatively multiplexing multiple bands (i.e., channels) in each bridge chip. In order to realize both a downlink and an uplink with lower power consumption, this paper presents a newly developed serial I/F with three key techniques: (1) PAM-4-based 4-channel (4-ch) multiplexing, (2) cascaded CDR circuits in (3) ring topology. The fabricated transceiver (TRX) for the proposed I/F achieves 3.69pJ/b with a BER lower than 10-15 at 25.Gb/s with PRBS31 through 1.84dB of channel loss at 6.4GHz. The proposed I/F can achieve a state-of-the-art FoM (defined as “# of packages × Data Rate / power consumption”) of 1.80PKG.Gb/s/mW.

30.3 A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

1.2 V 0.2-to-6.3 GHz transceiver for a multimode radio is fabricated in a 0.13 mum CMOS technology is proposed. The transmitter achieves EVM of less than -29.5 dB at -3 dBm output from 0.2 to 7.2 GHz while consuming 69 mW, where the modulation scheme used is equivalent to 802.11a, 54Mb/s mode. Without any explicit matching components, S22 and S11 are kept less than -9.5 dB and -9.2 dB, respectively, over the frequency range from 0.1 to 6.3 GHz. To achieve wideband output matching, a parallel combination of a common-source amplifier and a source-follower buffer is used. This structure copes with both 50 Omega output resistance, and small output capacitance. The choke in the pre-power-amplifier (PPA) is also eliminated by adopting a push-pull amplifier and by using a modified envelope signal injection biasing scheme. The PPA achieves OP 1dB of 6 dBm, which corresponds to almost the rail-to- rail swing for 1.2 V power supply.

A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier

Mobile WiMAX complying with the IEEE 802.16e standard is one of the emerging standards and is achieving world-wide penetration. Low-cost implementation is essential and single-chip implementation is a straightforward approach. However, there are many technical challenges such as floor-planning, signal integrity and scalability of analog/RF circuits in an SoC, as well as power reduction in scaled CMOS technologies. In this work, we have designed and fabricated a fully-integrated 2RX × 1TX dual-band direct-conversion transceiver having digital interfaces for a mWiMAX SoC in a 65nm pure CMOS technology. To cope with the constraints of floor-planning while maintaining the signal integrity, inductorless local oscillator (LO) distribution using compact dual-mode fractional dividers is introduced, leading to the reduction of die area. Total noise figure of 3.8dB is achieved by a novel noise-shaping transimpedance amplifier to mitigate the flicker noise of a scaled CMOS device.

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS

A broadband low-noise amplifier (LNA) in a 0.13 mum CMOS is presented. The LNA consists of two cascaded gain stages. The first stage is a resistive feedback amplifier for an input impedance matching, and the second stage is an inductive peaking amplifier for gain compensation. Measurement results exhibit a voltage gain of 14 dB and a gain variation less than 1.7 dB over the frequency range of 0.1 to 6.0 GHz. Its input return loss is below -8.3 dB and the noise figure is 4.0 to 4.7 dB across the bandwidth. The LNA consumes 16 mW from a 1.2 V supply and occupies 0.13 mm2.

Junji Wadatsumi

Papers

A Fully Integrated 2 $\times$ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS

30.3 A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS

A 1.2V, 0.1-6.0 GHz, Two-Stage Differential LNA Using Gain Compensation Scheme