Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.

Progress and challenges in VLSI placement research

During the IC design process, functional specifications are often modified late in the design cycle, after placement and routing are completed. However, designers are left either to manually process such modifications by hand or to restart the design process from scratch — a very costly option. In order to address this issue, we present DeltaSyn, a method for generating a highly optimized logic difference between a modified high-level specification and an implemented design. DeltaSyn has the ability to locate boundaries in implemented logic within which changes can be confined. Delta-Syn demarcates the boundary in two phases. The first phase employs fast functional and structural analysis techniques to identify equivalent signals forming the input-side boundary of the changes. The second phase locates the output-side boundary of the changes through a novel dynamic algorithm that detects matching logic downstream from the changes required by the ECO. Experiments on industrial designs show that together these techniques successfully implement ECOs while preserving an average of 97% of the existing logic. Unlike previous approaches, the use of bit-parallel logic simulation and fast SAT solvers enables high performance and scalability. DeltaSyn can process and verify a typical ECO for a design of around 10K gates in about 200 seconds or less.

DeltaSyn: an efficient logic difference optimizer for ECO synthesis

Given the significance of placement in integrated circuit (IC) physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress leading up to the state of the art, and outstanding challenges.

Progress and Challenges in VLSI Placement Research

This paper introduces a new algorithm for Boolean factoring. The proposed approach is based on a novel synthesis paradigm, functional composition, which performs synthesis by associating simpler sub-solutions with minimum costs. The method constructively controls characteristics of final and intermediate functions, allowing the adoption of secondary criteria other than the number of literals for optimization. This multi-objective factoring algorithm presents interesting features and advantages when compared to previous works.

Boolean factoring with multi-objective goals

This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the concept of factor cuts is extended to kl-cuts. Algorithms for computing this kind of cuts, including kl-cuts with unbounded k, are presented and results are shown. As a practical application, a covering algorithm using these cuts is presented.

https://www.lume.ufrgs.br/bitstream/handle/10183/26503/000759632.pdf;sequence=1

KL-cuts: a new approach for logic synthesis targeting multiple output blocks

We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We show how to adapt this algorithm to logic optimization for timing correction at late stages of VLSI physical design and report experimental results on recent industrial chips. By restructuring long critical paths, our code achieves worst-slack improvements of up to several hundred picoseconds on top of traditional timing optimization techniques.

Timing optimization by restructuring long combinatorial paths

Delay optimization of linear depth boolean circuits with prescribed input arrival times

The delay of circuits whose inputs have specified arrival times

For some k>=2 let d=(d"1,d"2,...,d"k)@?R">"0^k. We denote the concatenation of k vectors a"1,a"2,...,a"[email protected][email protected]?"n">="0R^n by a"1a"2...a"k and use @e to denote the empty vector. We consider a recursively defined function D"d:@?"n">="0R^n->[email protected]?{-~} with D"d(@e)=-~, D"d((a))=a for [email protected]?R and D"d(a)=min{max{D"d(a"i)+d"i|[email protected][email protected]?k}|a=a"1a"2...a"k with a"[email protected][email protected]?m=0n-1R^m for [email protected][email protected]?k} for [email protected]?R^n with n>=2. The function D"d equals the cost of an optimal alphabetic code tree with unequal letter costs and the above recursion naturally generalizes a recursion studied by Kapoor and Reingold [S. Kapoor, E.M. Reingold, Optimum lopsided binary trees, J. Assoc. Comput. Mach. 36 (1989) 573-590]. If z(n) denotes the vector consisting of n>=0 zeros, then let f(@a)=max{[email protected]?N"0|D"d(z(i))@[email protected]} for @[email protected]?R. Let d=min{d"1,d"2,...,d"k} and D=max{d"1,d"2,...,d"k}. Our main result is that D"d(z(@?i=1nf(a"i)))@?D"d(a)@?D"d(z(@?i=1nf(a"i)))+6D-2d for a=(a"1,a"2,...,a"n)@?R">="0^n. This result is useful for the analysis of the asymptotic growth of D"d.

Jürgen Werber

Papers

Timing optimization by restructuring long combinatorial paths

Delay optimization of linear depth boolean circuits with prescribed input arrival times

The delay of circuits whose inputs have specified arrival times

On the cost of optimal alphabetic code trees with unequal letter costs