Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Calibration methods and circuits for optimized on-die termination

Integrated processing of multimedia signals can eliminate unnecessary signal processors and converters without losing the functionality of typical home entertainment system components. The integrated multimedia system includes a main player that captures and processes signals digitally. The main player may adjust the audio signal to provide audio output of equal loudness across all frequencies by accounting for sensitivity of the human ear for sounds of varying frequencies. The main player can also account for perceived differences in loudness based on the angle of a listener to a speaker by detecting the position of a user and making an adjustment accordingly. The invention further provides a speaker that has embedded performance characteristics or an identifier that allows the system to provide an optimal speaker driving current for a particular system or determine how that speaker would be best implemented in the integrated system.

Integrated multimedia signal processing system using centralized processing of signals

A personal audio device, such as a wireless telephone, includes an adaptive noise canceling (ANC) circuit that adaptively generates an anti-noise signal from a reference microphone signal and injects the anti-noise signal into the speaker or other transducer output to cause cancellation of ambient audio sounds. An error microphone is also provided proximate the speaker to measure the ambient sounds and transducer output near the transducer, thus providing an indication of the effectiveness of the noise canceling. A processing circuit uses the reference and/or error microphone, optionally along with a microphone provided for capturing near-end speech, to determine whether the ANC circuit is incorrectly adapting or may incorrectly adapt to the instant acoustic environment and/or whether the anti-noise signal may be incorrect and/or disruptive and then take action in the processing circuit to prevent or remedy such conditions.

Oversight control of an adaptive noise canceler in a personal audio device

The present invention provides methods and systems for digitally processing audio signals. Some embodiments receive an audio signal and converting it to a digital signal. The gain of the digital signal may be adjusted a first time, using a digital processing device located between a receiver and a driver circuit. The adjusted signal can be filtered with a first low shelf filter. The systems and methods may compress the filtered signal with a first compressor, process the signal with a graphic equalizer, and compress the processed signal with a second compressor. The gain of the compressed signal can be adjusted a second time. These may be done using the digital processing device. The signal may then be output through an amplifier and driver circuit to drive a personal audio listening device. In some embodiments, the systems and methods described herein may be part of the personal audio listening device.

System and method for digital signal processing

A personal audio device, such as a wireless telephone, includes an adaptive noise canceling (ANC) circuit that adaptively generates an anti-noise signal from a reference microphone signal and injects the anti-noise signal into the speaker or other transducer output to cause cancellation of ambient audio sounds. An error microphone is also provided proximate the speaker to estimate an electro-acoustical path from the noise canceling circuit through the transducer. A processing circuit determines a degree of coupling between the user's ear and the transducer and adjusts the adaptive cancellation of the ambient sounds to prevent erroneous and possibly disruptive generation of the anti-noise signal if the degree of coupling lies either below or above a range of normal operating ear contact pressure.

Ear-coupling detection and adjustment of adaptive response in noise-canceling in personal audio devices

An audio path is constructed to include a multi-bit sigma-delta converter for converting an N-bit digital input to an n-bit output representing an over-sampled, lower resolution n-bit version of the N-bit digital input; a formatter for converting the n-bit output to an m signal output (e.g., as a thermometer code, a SDM format or a PWM format); an m-by-m switching matric for receiving the m output signals and for reordering the m output signals, m class-D drivers individual ones of which are driven by one of the reordered m output signals for driving one of m speakers; and a dynamic element matching (DEM) block coupled to the switching matric for controlling the reordering of the m output signals driving the m class-D drivers for spreading the distortion due at least to driver-speaker pair mismatch to wide band noise. The DEM may operate to generate white noise, or it may generate shaped (colored) noise.

Method and apparatus for implementing a class D driver and speaker system

An N-level quantizer circuit (14) has an analog input terminal and N-1 digital output terminals, and includes a sampling circuit (SW samp) coupled to the input terminal for providing a sampled input voltage signal; at least one preamplifier stage (14A) for converting the sampled input voltage signal to a current signal and providing an amplified sampled input signal; and N-1 comparator stages (14B) each having an input coupled to an output of the at least one preamplifier stage (14A) and sharing the input current equally. Individual ones of the N-1 comparator stages (14B) operate to compare the amplified sampled signal to an associated one of N-1 reference signals. The quantizer (14) further includes N-1 latches (14C), individual ones of which latch an output state of one of the N-1 comparators and have an output coupled to one of the N-1 digital output terminals of the quantizer circuit (14).

Low capacitance, low kickback noise input stage of a multi-level quantizer with dithering and multi-threshold generation for a multi-bit sigma-delta modulator

A multilevel quantizer (14) is provided in combination with dynamic element matching DEM (20) circuitry in a multibit sigma-delta modulator (10). The DEM circuitry is implemented in a divided manner as two major component parts: at least one current mode DEM switch matrix (20B)(SM), and an associated DEM decision logic block that implements the DEM control algorithm (20A) and that controls the SM. The DEM decision logic block is removed from the delay sensitive sigma-delta feedback loop, while the DEM SM remains within the feedback loop. Also described is a convenient and efficient technique to implement the DEM SM, using current steering logic within the multibit quantizer. In this case one or more DEM switching matrices may be provided within the quantizer for reordering the N-1 digital output bits of the N-level quantizer.

A multi-level quantizer with current mode DEM switch matrices and separate DEM decision logic for a multibit sigma delta modulator

A multi-mode I/0 circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/0 circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC.

Multi-mode I/O circuitry supporting low interference signaling schemes for high speed digital interfaces

Disclosed is a method for charging a battery and circuitry for performing the method. The method includes steps of: (A) generating at a first node a battery charge current (Icharge) for charging the battery; (B) generating at a second node a replica current (Irep) from Icharge, where Irep<Icharge; and (C) operating a closed loop current sink for sinking Irep, where a digital output of said closed loop current sink is a measure of the magnitude of Icharge. In the preferred embodiment the digital output is input to a control circuit for controlling the generation of Icharge. Also in the preferred embodiment the closed loop current sink is constructed from a multi-stage DAC that is driven by an output of an n-level digital filter that is incremented or decremented as a function of a voltage difference between the first node and the second node. Preferably the multi-stage DAC is a multi-stage current steering DAC, and the n-level digital filter is constructed using an up/down counter. A selection of stages of the multi-stage DAC to be turned off and on is made by a DEM logic block that is interposed between the output of the counter and the multi-stage DAC. The disclosed circuitry and method may be extended for providing a battery discharge measurement circuit for enabling a battery capacity test to be performed.

Method and apparatus for measuring battery charge and discharg current using a direct analog-to-digital conversion of a charge/discharge replica current

Jussi-Pekka Tervaluoto

Papers

Method and apparatus for implementing a class D driver and speaker system

Low capacitance, low kickback noise input stage of a multi-level quantizer with dithering and multi-threshold generation for a multi-bit sigma-delta modulator

A multi-level quantizer with current mode DEM switch matrices and separate DEM decision logic for a multibit sigma delta modulator

Multi-mode I/O circuitry supporting low interference signaling schemes for high speed digital interfaces

Method and apparatus for measuring battery charge and discharg current using a direct analog-to-digital conversion of a charge/discharge replica current