Quality adaptation in a multisession multimedia system: model, algorithms, and architecture

A method and apparatus for producing an electronic circuit which allows a device to be connected to a bus, such as a system bus in a computer. The invention accepts user specified parameters for configuring a device adapter which interfaces the device to the bus, and thereafter generates a customized device adapter based on such user specified parameters. By using a common design macro, which is programmable, a user can easily specify and generate custom device adapters for a plurality of dissimilar devices to be connected to the bus. A resulting adapter architecture allows for multiple, dissimilar devices to interface to a computer bus with a single device adapter integrated circuit or card.

Multi-device adapter card for computer

A computerized design system is employed for designing product specifications for a multitude of products. This computerized design system uses an input from a user to define a series of goals and from these goals to create a data structure which is extracted from the goals. This data structure is then topologically stored in a computer memory which is then used to create a mapping between requirement specifications and a conceptual design. An output is then provided which can be used as a final design specification.

System design method

In this work, we investigate state-retentive power gating of register files for leakage reduction in multicore processors supporting multithreading. In an in-order core, when a thread gets blocked due to a memory stall, the corresponding register file can be placed in a low leakage state through power gating for leakage reduction. When the memory stall gets resolved, the register file is activated for being accessed again. Since the contents of the register file are not lost and restored on wakeup, this is referred to as state-retentive power gating of register files. While state-retentive power gating in single cores has been studied in the literature, it is being investigated for multicore architectures for the first time in this work. We propose specific techniques to implement state-retentive power gating for three different multicore processor configurations based on the multithreading model: 1) coarse-grained multithreading, 2) fine-grained multithreading, and 3) simultaneous multithreading. The proposed techniques can be implemented as design extensions within the control units of the in-order cores. Each technique uses two different modes of leakage states: low-leakage savings and low wake-up and high-leakage savings and high wake-up latency. The overhead due to wake-up latency is completely avoided in two techniques while it is hidden for most part in the third approach, either by overlapping the wake-up process with the thread context switching latency or by executing instructions from other threads ready for execution. The proposed techniques were evaluated through simulations with multiprogrammed workloads comprised of SPEC 2000 integer benchmarks. Experimental results show that in an 8-core processor executing 64 threads, the average leakage savings were 42 percent in coarse-grained multithreading, while they were between seven percent and eight percent for finegrained and simultaneous multithreading.

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State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores

Advances in distributed system technology have enabled new computation paradigms such as Grid, Cloud, and Internet computing. Due to the logical and physical organization of these paradigms, portable and embedded computing devices are being developed and naturally becoming an integral part of these systems. In addition to stringent area and power requirements, design constraints such as time-to-market and competitive margin pose serious challenges to embedded hardware designers. One of the most promising avenues to overcome these challenges is reconfigurable hardware. In this work, FPGA-based reconfigurable hardware is examined. As a case study, Principal Component Analysis (PCA), the classical technique to reduce the dimensionality of data and to extract dominant features, is designed and implemented as hardware on FPGA to be reconfigured dynamically during execution. Using part of a handwriting analysis application together with a benchmark dataset, experiments are performed to evaluate the feasibility, efficiency, and flexibility of reconfigurable hardware.

FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications

In Web mining applications, an enormous amount of data needs to be processed quickly and efficiently. Thus, hardware support is crucial to enhance the performance of these operations. We are investigating on-chip hardware support for web mining operations. In this work, we introduce chip level hardware support for similarity measure computation. We have implemented both the software and hardware versions of various similarity measures using a hierarchical platform-based design approach to facilitate component reuse at different levels of abstraction. Software modules are executed on a reconfigurable soft processor core on the same field programmable gate array (FPGA) as the hardware implementations for performance comparison purpose. Our experimental results show that the performance of web mining operations could be significantly enhanced by using on-chip hardware.

On-Chip Hardware Support for Similarity Measures

The following k-way graph partitioning (GP) problem is considered: given an undirected weighted graph G(V,E), partition the nodes of G into k parts of almost equal size such that the partition-cost (sum of the weights on edges with nodes in different parts) is minimized. Two simple and fast algorithms are proposed, namely, direct algorithm AUCTION and iterative algorithm GREEDYCYCLE. In algorithm AUCTION, the idea of using auction and biddings is introduced using the master-workers paradigm. Algorithm GREEDYCYCLE is a greedy algorithm where the idea of cyclic node passing among parts during the iterative improvement stage is introduced. Cyclic node passing is a k-way generalization of the 2-way node exchange found in the Kernighan-Lin (1970) approach. Experimental results show that, as compared to the existing algorithms, these algorithms are extremely fast, and they produce solutions of reasonable quality.

Fast graph partitioning algorithms

In Web mining applications, an enormous amount of data needs to be processed quickly and efficiently. Thus, hardware support is crucial to enhance the performance of these operations. In this work, chip-level hardware support for similarity measure calculation is introduced and then extended to similarity matrix computation. Both software and hardware versions of various similarity computations are implemented with a hierarchical platform-based design approach to facilitate component reuse at different levels of abstraction. Software modules are executed on a reconfigurable soft processor core on the same field-programmable gate array (FPGA) as the hardware implementations for the purpose of performance comparison. Preliminary results using parallel hardware are also presented. In addition, performance gain from hardware as opposed to a general-purpose processor is examined. Experimental results show that the performance of similarity computation for a set of feature vectors could be significantly enhanced by using on-chip hardware.

Hardware acceleration for similarity computations of feature vectors

This paper presents the JAFARDD (a Java Architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing) processor. JAFARDD dynamically translates Java stack-dependent bytecodes to RISC-style stack-independent instructions to facilitate the use of a general-purpose RISC core. JAFARDD enables the exploitation of instruction level parallelism among the translated instructions by the use of bytecode folding coupled with Tomasulo's algorithm. We detail the JAFARDD architecture and the global architecture design principles observed while designing each pipeline module. We also illustrate the flow of the Java bytecodes through each of the processing phases. Benchmarking of JAFARDD using SPECjvm98 has shown a performance improvement between 1.10 and 2.25.

The JAFARDD Processor: A Java Architecture Based on a Folding Algorithm, with Reservation Stations, Dynamic Translation, and Dual Processing

Hypercycles, a class of multidimensional graphs that are generalizations of the n-cube are presented. These graphs are obtained by allowing each dimension to incorporate more than two elements and a cyclic interconnection strategy. Hypercycles offer simple routing and the ability, given a fixed degree, to choose among a number of different size graphs. These graphs can be used in the design of interconnection networks for distributed systems tailored specifically to the topology of a particular application. A back track-to-the-origin-and-retry routing, whereby paths that block at intermediate nodes are abandoned and a new attempt is made, is presented. Intermediate nodes are chosen at random at each point from among those that form the shortest paths from a source to a destination. Simulation results that establish the performance of a variety of configurations are presented. An initial attempt at constructing a hypercycle-based router is discussed. >

K.F. Li

Papers

On-Chip Hardware Support for Similarity Measures

Fast graph partitioning algorithms

Hardware acceleration for similarity computations of feature vectors

The JAFARDD Processor: A Java Architecture Based on a Folding Algorithm, with Reservation Stations, Dynamic Translation, and Dual Processing

Performance evaluation of the backtrack-to-the-origin-and retry routing for hypercycle-based interconnection networks