Since the first integrated circuits in the late 1950s, the semiconductor industry has enjoyed exponential growth This observation is illustrated by Moore’s law which states that the number of transistors that can be placed on an integrated circuit (chip) doubles roughly every two years Other examples of approximately exponential behavior are the increase in clock speed at which digital circuits run and the decrease in size of features that can be printed by manufacturing equipment Due to improvements in manufacturing technology, the performance of chips is increasingly determined by the lengths of the wires that connect the functional elements of a chip These wires are realized (routed) very late in the design flow Mismatch between routing resources and routing demand is known as congestion and can lead to detoured wires and too many vias Such surprises usually have detrimental effect on performance and yield and should be avoided In order to prevent routing problems later on, congestion needs to be considered at earlier stages of the design flow than is traditionally the case Congestion maps display congestion hotspots, and are a means to communicate (potential) resource conflicts In this thesis, two methods for fast estimation of such maps are proposed The first uses a probabilistic approach, and the second is essentially a global router with focus on speed rather than overflow minimization Using such methods, algorithms earlier in the design flow can take routing considerations into account without the need to actually invoke the routers, allowing for more effective and accurate decisions and optimizations Many algorithms require that multi-pin connections are broken down into two-pin connections This thesis introduces the concept of routing freedom for measuring the amount of flexibility in such connections and decompositions In the face of uncertainty about what will happen later on in the design flow, it can be beneficial to create as much flexibility as possible Unfortunately, more freedom also corresponds to more vias under certain conditions This thesis demonstrates how freedom analysis can be used to optimize net decomposition using Steiner tree algorithms and improve global routing During chip implementation there are typically multiple considerations Important examples are congestion, vias and run time Equivalently, (heuristic) algorithms may base decisions on several criteria In this thesis, tiebreakers are used to deal with such situations instead of more traditional approaches based on weights This approach is used extensively in a net decomposition algorithmand during global routing The problems encountered in chip implementation are huge in size and complexity Often, approaches without guarantee of optimality are therefore used, as is the case for many of the algorithms presented in this thesis Such approaches need to be validated and compared by benchmarking Therefore, an extensive software package implementing the ideas presented in this thesis has been developed A large number of experiments have been conducted demonstrating the effectiveness and limitations of the proposed methods and the tradeoffs that need to be made

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Congestion analysis and management

Because of the mask error enhancement factor (MEEF), iso-dense biases of mask patterns are amplified when the image is transferred to a wafer. A slight critical-dimension (CD) difference between an OPC test mask and an OPCed mask may cause a significant OPC error on the wafer. The impact of the mask CD error on OPC accuracy has never been evaluated, however, to evaluate the impact of the inter-mask CD error (IMCDE), we measured the CD errors of various line-and-space patterns on attenuated phase-shifting masks for ArF exposure. We investigated the effect of IMCDE and the iso-dense biases of test-mask patterns on OPC accuracy. We found that a degree of IMCDE is tolerable in attenuated phase-shifting ArF masks. This tolerable degree of IMCDE is useful to gauge the effectiveness of the OPC, with an eye to developing a lithographic process for semiconductor production. Furthermore, based on experimental results showing that a wafer CD is controllable when scanner conditions such as numerical aperture (NA) and partial coherence factor (sigma) are optimized, a new mask-matching method to compensate for the IMCDE is proposed.

Impact of inter-mask CD error on OPC accuracy for resolutions of 90 nm and below

An automatic system that combines actions in both the image domain as well as in the layout-database domain for
accurate mask-defect analysis and application of design criticality will be presented. In this paper we will emphasize the
qualification and calibration of the system and its various pieces of functionality with the use of programmed defect
masks and low-voltage mask CD-SEM measurement data. Results on 1D and 2D programmed defects of various natures
are reported in dense layout as well as in real memory design layout. The results show that the system can accurately
extract mask CD-errors and defect sizes at a resolution far below that of the pixel-size of state-of-the-art mask-defect
inspection tools at nanometer resolution.
We will further demonstrate that mask-defect-inspection data can contain optical anomalies when defect or residual
feature sizes are smaller than the inspection wavelength. Mask inspection images then no longer show the real defect.
These anomalies can be analyzed with the system using advanced image actions.
Finally, we will demonstrate the capability to calculate the effects that defects have on final wafer printability even
without the need for input layout. Hence, model-based defect properties can be combined with rule-based defect
properties as well as multi-layer, design-based criticality-region properties for utter flexibility in defect disposition
capability.

K. G. Haens

Papers

DFM software for photomask production and qualification of its accuracy and functionality