Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

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A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

On January 2, 1997, the National Institute of Standards and Technology in the US announced that they intend to initiate the development of a new world-wide encryption standard to replace the Data Encryption Standard (DES). A call for candidates was announced worldwide with the deadline of 15th June 1998. Totally, 15 candidates were submitted from the US, Canada, Europe, Asia and Australia. The author is the designer of one of the candidates, and a codesigner of another proposal. The AES proposals are required to support at least a block size of 128 bits, and three key sizes of 128, 192, and 256 bits. The hope of NIST is that the end result is a block cipher “with a strength equal to or better than that of Triple-DES and significantly improved efficiency.” In March 1999 the first AES workshop was held in Rome, Italy. August 9, 1999, NIST announced the selection of five candidates for a final round of analysis. After a second AES workshop to be held in New York in April 2000, NIST intends to make a final selection of one or two algorithms for the Advanced Encryption Standard during the summer of year 2000. The five algorithms selected to the final round are MARS, RC6, Rijndael, Serpent, and Twofish, which also are the candidates predicted by the author in a letter to NIST. The winner(s) of the AES competition are likely to be used widely and for many years to come. Therefore, it is important that a candidate is chosen with a high level of security not only now, but also in 25 years time or more. It is of course impossible to predict which of the five candidates will survive attacks for such a long period, but this also speaks in favor of the choice of a candidate with a large security margin. All AES candidates are iterated ciphers, where a ciphertext is computed as a function of the plaintext (and possibly some previous ciphertexts) and the key in a number of rounds. In the call for candidates NIST did not allow for a variable number of rounds. Although NIST allowed for possible “tweaks” (small changes), at the end of the first round (April 15, 1999) none of the designers changed the number of rounds of their algorithms. In fact of the five final ones, only the MARS designers suggested a modification to overcome a small key-schedule problem. In our opinion, the number of rounds fixed by some of the designers is too small, and the algorithms will prove inadequate for long-term security. We believe that this narrows down the five candidates to only a few. M. Walker (Ed.): IMA Crypto & Coding’99, LNCS 1746, pp. 185–185, 1999. c © Springer-Verlag Berlin Heidelberg 1999

Advanced Encryption Standard (AES) - An Update.

With the increase in computation and data storage in cloud servers, the need for a dedicated hardware accelerator for encryption is arising in order to reduce the processor job. High-throughput and resource-optimized implementation of 128-bit Advanced Encryption Standard (AES 128-bit), which can be used as an accelerator, is presented in this article. Memory partitioning is done in order to assign multiple ports for parallel data access. After the algorithm is pipelined and unrolled at each operation on the basis of the analyzed latency and initiation interval of different operations, for each critical path delays, a new multistage single initiation interval sub-pipelined architecture is proposed to make the initiation interval to one for lowest path delay. As a result, all operations in AES can be initiated within one clock cycle and can accept input in every clock cycle. The proposed method when simulated, synthesized, and implemented on the latest XC7VX690T device gives a throughput of 104.06 Gbps at a maximum frequency of 813 MHz and 1.23-ns path delay. The resource utilization is lower when compared with other counterparts. The proposed system gives 30.74 Mbps efficiency on XC5VLX85 device, which is 27.13% more than the best efficiency reported in a previous work.

AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

Cloud computing is a technology in which the resources are delivered as services. Users can access them anywhere, anytime via the Internet without any need to know the infrastructure knowledge, experience, or even authority that provides such services. It has become an important medium for enterprises to develop their networks because of these resources. With the growing need for cloud computing, security is becoming important for both individuals and business needs. Many researchers have studied the security of cloud computing. Still, security gaps or threats are increasing as the demand for cloud computing connectivity increases. Because a third party mostly provides cloud platforms to the cloud client, data protection in the cloud is the primary issue. This paper presents a novel, effective lightweight homomorphic cryptographic algorithm which contains two layers of encryption. The first layer uses the new effective, light-weight cryptographic algorithm and the second layer multiplicative homomorphic schemes considered for improving security data in cloud computing. This approach offers both symmetric and asymmetric cryptography features. The proposed approach's performance is evaluated using a variety of metrics, including memory, computational time and (key sensitivity), statistical analysis, image histogram, and entropy change analysis. The proposed algorithm's experimental findings showed a high level of security and an apparent improvement in encryption execution time, memory usage, and throughput. When compared to the cryptographic systems widely used in cloud computing. 

A Novel Effective Lightweight Homomorphic Cryptographic Algorithm for data security in cloud computing

The lightweight cryptography (LWC) is an interesting research area in the field of information security. So, different lightweight mechanisms have been developed in the existing works for securing the confidential information. But, it remains with the limitations like increased components usage, time consumption, power consumption and memory requirement. Also, the existing techniques utilized the same type of key generation and pattern generation approaches for all kinds of data, which leads to reduced security. To solve these problems, this paper intends to develop a new LWC mechanism by using the differential logical pattern (DLP) algorithm. Here, the input message (i.e. text or image) with the size of 16 × 16 blocks is taken for processing. For this input, the random key and S-box are generated for extracting the patterns. Then, the DLP mechanism is utilized to encrypt the input blocks before transmitting it to the receiver. At the receiving side, the inverse random key and S-box generation mechanisms are applied to generate the key used for decryption. Finally, the DLP decryption mechanism is applied to reconstruct the original data sent by the sender. The benefits of this work are reduced memory consumption and time complexity. The experimental results evaluate the performance of this technique by using various measures such as Peak Signal to Noise Ratio, Mean Squared Error, correlation coefficient, Number of Pixels Change Rate, Unified Average Changing Intensity, CPU cycles, time and memory.

A Lightweight Cryptography Technique with Random Pattern Generation

Power efficient and high performance VLSI architecture for AES algorithm

With the growing importance of electronic products in day-today life, the need for portable electronic products with low power consumption largely increases. In this paper, an area efficient high speed and low power Multiply Accumulator unit (MAC) with carry look-ahead adder (CLA) as final adder is being designed. In the same MAC architecture design in final adder stage of partial product unit the carry save adder(CSA), carry select adder(CSLA) and carry skip adder(CSKPA) are also used instead of CLA to compare the power and performance. These MAC designs were simulated and synthesized using Xilinx 8.1. The simulation result shows that the MAC design with CLA has area reducing by 16.7%, speed increase by 1.95% and the consumed power reducing by 0.5%.

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K. Kalaiselvi

Papers

Power efficient and high performance VLSI architecture for AES algorithm

Area Efficient High Speed and Low Power MAC Unit