This paper studies the design and implementation of finite-impulse response (FIR) and infinite-impulse response (IIR) variable digital filters (VDFs), whose frequency characteristics can be controlled continuously by some control or tuning parameters. A least squares (LS) approach is proposed for the design of FIR VDFs by expressing the impulse response of the filter as a linear combination of basis functions. It is shown that the optimal LS solution can be obtained by solving a system of linear equations. By choosing the basis functions as piecewise polynomials, VDFs with larger tuning range than that of ordinary polynomial based approach results. The proposed VDF can be efficiently implemented using the familiar Farrow structure. Making use of the FIR VDF so obtained, an Eigensystem Realization Algorithm (ERA)-based model reduction technique is proposed to approximate the FIR VDF by a stable IIR VDF with lower system order. The advantages of the model reduction approach are: 1) it is computational simple which only requires the computation of the singular value decomposition of a Hankel matrix; 2) the IIR VDF obtained is guaranteed to be stable; and 3) the frequency response such as the phase response of the FIR prototype is well preserved. Apart from the above advantages, the proposed IIR VDF does not suffer from undesirable transient response during parameter tuning found in other approaches based on direct tuning of filter parameters. For frequency selective VDFs, about 40% of the multiplications can be saved using the IIR VDFs. The implementation of the proposed FIR VDF using sum-of-powers-of-two (SOPOT) coefficient and the multiplier block (MB) technique are also studied. Results show that about two-third of the additions in implementing the multiplication of the SOPOT coefficients can be saved using the multiplier block, which leads to significant savings in hardware complexity.

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On the design and implementation of FIR and IIR digital filters with variable frequency characteristics

This work studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semi-definite programming (SDP) problem, which allows zero magnitude constraint at /spl omega/=/spl pi/ to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches.

/pdf/the-design-and-multiplier-less-realization-of-software-radio-4efwsuhg5g.pdf

The design and multiplier-less realization of software radio receivers with reduced system delay

This article proposes an efficient implementation of the Farrow (1988) structure using sum-of-powers-of-two (SOPOT) coefficients and multiplier-block (MB). In particular, a novel algorithm for designing the Farrow coefficients in SOPOT form is detailed. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Using MB, the redundancy between multipliers can be fully exploited through the reuse of the intermediate results generated. Design examples show that the proposed method can greatly reduce the complexity of the Farrow structure while providing comparable phase and amplitude responses.

/pdf/on-the-design-and-efficient-implementation-of-the-farrow-1wz0e4nqlf.pdf

On the design and efficient implementation of the Farrow structure

This paper proposes two new methods for designing a class of two-channel perfect reconstruction (PR) finite impulse response (FIR) filterbanks (FBs) and wavelets with K-regularity of high order and studies its multiplier-less implementation. It is based on the two-channel structural PR FB proposed by Phoong et al (1995). The basic principle is to represent the K-regularity condition as a set of linear equality constraints in the design variables so that the least square and minimax design problems can be solved, respectively, as a quadratic programming problem with linear equality constraints (QPLC) and a semidefinite programming (SDP) problem. We also demonstrate that it is always possible to realize such FBs with sum-of-powers-of-two (SOPOT) coefficients while preserving the regularity constraints using Bernstein polynomials. However, this implementation usually requires long coefficient wordlength and another direct-form implementation, which can realize multiplier-less wavelets with K-regularity condition up to fifth order, is proposed. Several design examples are given to demonstrate the effectiveness of the proposed methods.

https://hub.hku.hk/bitstream/10722/42960/1/90027.pdf

New design and realization techniques for a class of perfect reconstruction two-channel FIR filterbanks and wavelets bases

This paper studies the design, signal round-off noise, and complexity optimization of a new digital intermediate frequency (IF) architecture for a software radio receiver (SRR). The IF under study consists of digital filters with fixed coefficients, except for a limited number of multipliers required in the Farrow-based sampling rate converter (SRC). The fixed-coefficient filters can be implemented efficiently using sum-of-power-of-two (SOPOT) coefficients and the multiplier-block technique, which gives minimum adder realization. Apart from the multipliers required in the SRC, the digital IF can be implemented without any multiplications. While most multiplier- less filter design and realization methods address only the coefficient round-off problem by minimizing the number of SOPOT terms used, the proposed design methodology aims to minimize more realistic hardware complexity measure, such as adder cells and registers, of the digital IF subject to a given spectral and accuracy specifications. The motivation is that the complexity is closely related to the target output accuracy, which is specified statistically by its total output noise power generated by rounding the intermediate data. Two novel algorithms for optimizing the internal wordlengths of linear time-invariant systems are proposed. The first one relaxes the solution to real valued and formulates the design problem as a constrained optimization. A closed-form solution can be determined by the Lagrange multiplier method. The second one is based on a discrete optimization method called the Marginal Analysis method, and it yields the desired wordlengths in integer values. Both approaches are found to be effective and suitable to large scale systems. A design example and the field programmable gate array (FPGA) realization of a multi-standard receiver are given to demonstrate the proposed method

/pdf/design-and-complexity-optimization-of-a-new-digital-if-for-4jmb82yvjv.pdf

Design and Complexity Optimization of a New Digital IF for Software Radio Receivers With Prescribed Output Accuracy

Fractional-delay digital filter (FD-DF), implemented using the Farrow (1988) structure, is very attractive in providing online tuning delay of digital signals. This paper proposes a new method for the design of such Farrow-based FD-DF using sum-of-powers-of-two (SOPOT) coefficients. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Design examples show that the proposed method can greatly reduce the design time and complexity of the Farrow structure while providing comparable phase and amplitude responses.

/pdf/an-efficient-design-or-fractional-delay-digital-fir-filters-4xruincwtl.pdf

An efficient design or fractional-delay digital FIR filters using the Farrow structure

This paper proposes a novel algorithm for the design and hardware reduction of a class of multiplier-less two-channel perfect reconstruction (PR) filter banks (FB) using sum-of-powers-of-two (SOPOT) coefficients. It minimizes a more realistic hardware cost, such as adder cells, subject to a prescribed output accuracy taking account of rounding and overflow effects, instead of using just the SOPOT terms as in conventional methods. Furthermore, by using multiplier blocks (MB) to implement the filters in the FBs, significant overall saving in hardware resources can be achieved. An effective random search algorithm is also proposed to solve the design problem, which is also applicable to PR IIR FBs with highly nonlinear objective functions. Perfect reconstruction multirate filter have important applications in signal analysis, signal coding and the design of wavelet bases.

/pdf/efficient-design-of-a-class-of-multiplier-less-perfect-3hsme7hoca.pdf

K.L. Ho

Papers

An efficient design or fractional-delay digital FIR filters using the Farrow structure

Efficient design of a class of multiplier-less perfect reconstruction two-channel filter banks and wavelets with prescribed output accuracy