A overview is given of Motorola's DSP96002, a digital signal processor that implements IEEE-standard floating-point arithmetic. It is designed for graphics, image processing, spectral analysis and scientific computing applications. Performance peaks at 40.5 Mflops (million floating-point operations per second) and 13.5 MIPS (million instructions per second) and 18 Mflops on assembly-language benchmarks. The DSP is software-compatible with the fixed-point 56000/1 family architecture and instruction set. The 96002 achieves compatibility with other processors and databases, higher mathematical accuracy, and better error handling than implementations that do not conform to the IEEE standard. The 96002's on-chip memories, dual-bus architecture, and transparent DMA are suitable for multiprocessor systems in which many 96002s connect with minimum external components. These features result in a smaller-footprint, lower-cost system than other microprocessors or data-path chips. On-chip support for the fast access modes of external memories achieves near-SRAM (static random-access memory) performance with high-density DRAM/VRAM (dynamic RAM/virtual RAM) devices. An on-chip circuit emulation controller provides full access and control of the machine state for system debugging. A variety of software and hardware development tools support the 96002. >

A digital signal processor with IEEE floating-point arithmetic

A new digital signal processor (DSP) architecture is presented. This DSP consists of the usual components, such as instruction set, buses, data memories, execution unit, address generators, sequencer, and direct memory access controller, optimized for video signal processing. A 24-bit 50-ns DSP called the digital image signal processor (DISP) has been developed using 1- mu m CMOS technology. The performance of the DSP is evaluated by a benchmark test based on an actual video coding sequence. A multi-DSP configuration for a video codec that allows flexible algorithms and variable picture formats is studied. A low-bit-rate motion video codec can be built very easily using the DSPs presented by the authors. >

http://ieeexplore.ieee.org/iel1/31/1684/00044342.pdf

A DSP architectural design for low bit-rate motion video codec

A data processing device for registers which can be formatted as segments containing numbers to which operations can be applied in SIMD fashion. In addition it is possible to perform operations which combine different segments of one register or segments at different positions in the different registers. By providing specially selected registers it is thus made possible to perform multidimensional separable transformations (like the 2-dimensional IDCT) without transposing the numbers in the registers.

Data processing device and method of computing the cosine transform of a matrix

A description is given of a dual-bus, user-programmable, CMOS digital signal processor that implements the IEEE 754-1985 standard for binary floating-point arithmetic. Peak performance is 13.5 MIPS and 40.5 MFLOPS with a 27 MHz clock. Designed for symmetric multiprocessing, the dual buses are programmable and functionally identical. CPU data, interrupts, and DMA blocks can be directly communicated between 96002s, without using any external memory. Circuitry on each external port identifies the fast access modes of dynamic memories, giving near-static RAM performance with low-cost DRAM/VRAM devices. The 96002 is based on a superset of Motorola'' DSP56000/1 fixed-point DSP architecture and is software-compatible with DSP56000/1 source code. >

The Motorola DSP 96002 IEEE floating-point digital signal processor

An integrated circuit comprises a microprocessor (1), a memory (2) and one or more internal peripherals (3) connected, firstly, to one another and, secondly, to circuits external (4) to this integrated circuit by means of connections circuits (5). The peripherals comprise circuits called options circuits (6) enabling the operation of these peripherals to be configured. For an operating session corresponding to putting of the integrated circuit into service, the operations of these peripherals are defined as a function of information elements stored in the the first part of the memory (7). The memory also has a second part (8) designed to store instructions that can be executed by the microcontroller. This configuration of the peripherals takes place when the integrated circuit is put into service, by the linking of said peripherals to said first part of the memory. This memory is of the programmable type. The circuits known as options circuits possess means for being configured by default for a particular mode of operation of the microprocessor of the integrated circuit called the programming mode. In this mode, this microprocessor is capable of writing in the first part of the memory.

Integrated circuit comprising a microprocessor, a memory and internal configurable peripherals

This paper describes the architecture and applications of the DSP56001, a RAM-based member of the Motorola DSP56000 family of high performance, user-programmable CMOS digital signal processors. The DSP56001 has 512 × 24 bits of program RAM and special on-chip bootstrap hardware to download user programs from an external memory or host processor. The DSP56001 also contains two 256 × 24 bit data RAM's and two 256 × 24 bit ROM lookup tables for Mu-law/A-law to linear data conversion and sine/cosine functions. The processor architecture and instruction set are highly parallel, executing 10.25 million instructions per second with a 20.5 MHz clock. Fixed point arithmetic is performed by a 24 × 24 bit, non-pipelined multiply-accumulator with 56 bit product accumulation. Extensive I/O capability is provided by a full-speed memory expansion port, a byte-wide host processor interface, an asynchronous serial communications interface and a time division multiplexed, synchronous serial interface.

The architecture and applications of the motorola DSP56000 digital signal processor family

The authors describe the implementation of real and complex FFT (fast Fourier transform) algorithms on the Motorola DSP96002. The DSP96002 is a general-purpose, dual-bus IEEE standard floating-point digital signal processor (DSP). At a 74-ns instruction cycle, the DSP96002 implements a 1024-point real FFT in 0.905 ms and a 1024-point complex FFT in 1.55 ms. This performance is achieved by calculating up to three floating-point results in a single instruction cycle, or 40.5 MFLOPS peak. A radix-2 FFT butterfly is executed every four cycles, an average of 33.75 IEEE MFLOPS. The instruction set and architecture of the DSP96002 provide the basis for efficient implementation of FFTs and other fast transforms, such as the discrete Walsh-Hadamard transform, discrete cosine transform, and discrete Hartley transform. >

K.L. Kloker

Papers

The Motorola DSP 96002 IEEE floating-point digital signal processor

The architecture and applications of the motorola DSP56000 digital signal processor family

Efficient FFT implementation on an IEEE floating-point digital signal processor