A simple model for the hot-electron degradation of MOSFET linear-current drive is developed on the basis of the reduction of the inversion-layer mobility due to the generation of interface states. The model can explain the observed dependence of the device hot-electron lifetime on the effective channel length and oxide thickness by taking into account both the relative nonscalability of the localized damage region and the dependence of the linear-current degradation on the effective vertical electric field E/sub eff/. The model is verified for deep-submicrometer non-LDD n-channel MOSFETs with L/sub eff/=0.2-1.5 mu m and T/sub ox/=3.6-21.0 nm. From the correlation between linear-current and charge-pumping degradation, the scattering coefficient alpha , which relates the number of generated interface states to the corresponding amount of inversion-layer mobility reduction, can be extracted and its dependence on E/sub eff/ determined. Using this linear-current degradation model, existing hot-electron lifetime prediction models are modified to account explicitly for the effects of L/sub eff/ and T/sub ox/. >

A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation

In a method of estimating the lifetime of a floating SOI-MOSFET, constants A and B, stress condition dependency Id t (S) of a drain current and stress condition dependency Isub(S) of a substrate current in a body-fixed SOI-MOSFET, and stress condition dependency Id f (S) of a drain current in the floating SOI-MOSFET are obtained from experiment to estimate lifetime τ f (S) from the following equation: ##EQU1## where W f represents a known channel width of the floating SOI-MOSFET.

Method of estimating lifetime of floating SOI-MOSFET

Reviews present understanding of the AC stress effect in n-MOSFETs, defining and parameterizing the AC stress model. The authors incorporate the AC hot-carrier model into a circuit-level hot-carrier reliability simulator, ADHOC, that works in concert with SPICE. Sources of on-chip voltage excursions above the nominal value of the power supply V/sub dd/ are explored, and this information is used to develop a set of design guidelines at the transistor level. The hot-carrier reliability of a broad class of basic circuit building blocks is then simulated and used as the basis for a comprehensive set of design guidelines at the transistor and circuit levels. >

Circuit design guidelines for n-channel MOSFET hot carrier robustness

A practical and accurate design-in-reliability methodology has been developed for designs on 90-65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes.

Design-in-Reliability Approach for NBTI and Hot-Carrier Degradations in Advanced Nodes

By considering the decomposition of water‐related bonds at the silicon/oxide interfaces, theoretical expressions for the hot‐electron induced interface state generation and threshold‐voltage shift are developed. Results demonstrate that the relation between the threshold‐voltage shift and the hot‐electron fluence needs not follow the power law. The developed expression of the threshold‐voltage shift is a function of the initial interface trap density, interface hardness, density of water‐related chemical bond, and the capture cross section of interface trap and can be used to explain most of the reported experiments. When the trapping rate and the generation rate are close to each other, a power law dependence of the threshold‐voltage shift will be observed in a wide range of injection fluence. However, if the trapping rate is greater than the generation rate or for a sample with large hardness and small initial trap density, a quasi‐saturation region is observed because of most of the interface trap being filled and the small amount of generated traps. Saturation of the threshold‐voltage shift will occur when most of the water‐related bonds are dissociated and the created traps are filled.

Generation of interface states at the silicon/oxide interface due to hot‐electron injection

An empirical model that describes the dependence of hot-carrier lifetime on the effective channel length of an n-channel MOSFET, allowing the estimation of the lifetimes of transistors of a given length based on data from a limited number of channel lengths, is presented. The model takes into account the localization of hot-carrier induced damage and shows that the size of the damaged region relative to the total length of the transistor is important in determining the effect of hot-carrier-damage-induced transistor characteristics. The results are integrated into two commonly used equations for hot-carrier lifetimes of MOSFETs of a given channel length under DC operation. The model is experimentally verified for MOSFETs of effective channel lengths between 0.45 and 2.7 mu m. >

K. Mistry

Papers

An empirical model for the L/sub eff/ dependence of hot-carrier lifetimes of n-channel MOSFETs