It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

/pdf/high-speed-cmos-circuit-technique-17vk8tzafb.pdf

High-speed CMOS circuit technique

Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.

/pdf/nora-a-racefree-dynamic-cmos-technique-for-pipelined-logic-1ri3lhzntm.pdf

NORA: a racefree dynamic CMOS technique for pipelined logic structures

The modem history of liquid crystals has been dominated by the development of electronic displays. These developments began in 1964, when Heilmeier of RCA Laboratories discovered the guest-host mode and the dynamic-scattering mode. He thought a wall-sized flat-panel color TV was just around the corner From that point on, twisted-nematic (TN) mode, super TN mode, amorphous-Si field-effect transistor and room-temperature liquid crystals were developed. In the beginning, liquid-crystal displays (LCDs) were limited to niche applications such as small-size displays for digital watches, pocket calculators, and small handheld devices. That all changed with the development of the notebook computer industry. In 1988, Washizuka et al. of Sharp Corporation demonstrated an active-matrix full-color full-motion 14-in display using a thin-film-transistor array. The electronics industries now recognized that Heilmeier's 25-year dream of a wall-hanging television had become reality. LCDs could be used to replace existing cathode ray tubes. Through the cooperation and competition of many electronics giants, the LCD industry was firmly established.

https://eti.pg.edu.pl/documents/176568/264302/procieee2002kawamotothehistoryofliquidcd.pdf

The history of liquid-crystal displays

New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

New single-clock CMOS latches and flipflops with improved speed and power savings

Develops a methodology for selecting and optimizing flip-flops for low-energy systems with constant throughput. Characterization metrics, relevant to low-energy systems are discussed, providing insight into timing and energy parameters at both the circuit and system levels. Transistor sizes are optimized for minimal delay under constrained energy consumption. This methodology is applied to characterization of various flip-flop styles and their comparison in 0.25 /spl mu/m CMOS technology under scaled supply voltages. A transmission-gate master-slave latch-pair has the largest internal race margin, lowest energy consumption, and has energy-delay product comparable to much faster pulse-triggered latches.

/pdf/analysis-and-design-of-low-energy-flip-flops-4737owkfwv.pdf

Analysis and design of low-energy flip-flops

A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail. The CMOS-LSI includes 3300 elements and has a chip size of about 200 mil square, operates at 6 V supply voltage, and dissipates power of about 1 mW at a clock frequency of 50 kHz.

K. Odagawa

Papers

Clocked CMOS calculator circuitry