The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. Over the past decade, analog design automation has progressed to the point where there are industrially useful and commercially available tools at the cell level-tools for analog components with 10-100 devices. Automated techniques for device sizing, for layout, and for basic statistical centering have been successfully deployed. However, successful component-level tools do not scale trivially to system-level applications. While a typical analog circuit may require only 100 devices, a typical system such as a phase-locked loop, data converter, or RF front-end might assemble a few hundred such circuits, and comprise 10 000 devices or more. And unlike purely digital systems, mixed-signal designs typically need to optimize dozens of competing continuous-valued performance specifications, which depend on the circuit designer's abilities to successfully exploit a range of nonlinear behaviors across levels of abstraction from devices to circuits to systems. For purposes of synthesis or verification, these designs are not tractable when considered "flat." These designs must be approached with hierarchical tools that deal with the system's intrinsic design hierarchy. This paper surveys recent advances in analog design tools that specifically deal with the hierarchical nature of practical analog and RF systems. We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit. Such techniques are critical to both verification and synthesis activities for complex systems. We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring the space of performance tradeoffs early in the design process. Finally, we briefly touch on recent ideas for accommodating models of statistical manufacturing variations in these tools and flows

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs

The paper describes the recent state of the art in hierarchy. This paper surveys recent advances in analog design tools that specifically deal with the hierarchical nature of practical analog and RF systems. We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit. Such techniques are critical to both verification and synthesis activities for complex systems. We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring the space of performance tradeoffs early in the design process. Finally, we briefly touch on recent ideas for accommodating models of statistical manufacturing variations in these tools and flows.

/pdf/hierarchical-modeling-optimization-and-synthesis-for-system-h6f6gtng0x.pdf

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs Small models, that represent the overall functioning of portions of large or complex circuits, can be generated by algorithms and used for system design and verification.

Injection locking is a nonlinear dynamical phenomenon that is often exploited in electronic and optical oscillator design. Behavioral modeling techniques for oscillators that predict this phenomenon accurately are of significant scientific and practical importance. In this paper, we propose a nonlinear approach for generating small phase-domain oscillator/voltage-controlled oscillator (VCO) macromodels that capture injection locking well. Our nonlinear phase-domain macromodels are closely related to recent oscillator phase noise and jitter theories, and can be extracted efficiently by algorithm from SPICE-level descriptions of any oscillator or VCO. Using LC and ring oscillators as test cases, we confirm the ability of nonlinear phase macromodels to capture injection locking, and also obtain significant computational speedups over full SPICE-level circuit simulation. Furthermore, we show that our approach is equally effective for capturing the dynamics of transition to locking, including unlocked tones and phase jump phenomena.

Capturing oscillator injection locking via nonlinear phase-domain macromodels

Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.

/pdf/generation-of-yield-aware-pareto-surfaces-for-hierarchical-1zlld80dme.pdf

Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

Trajectory methods sample the state trajectory of a circuit as it simulates in the time domain, and build macromodels by reducing and interpolating among the linearizations created at a suitably spaced subset of the time points visited during training simulations. Unfortunately, moving from simple to industrial circuits requires more extensive training, which creates models too large to interpolate efficiently. To make trajectory methods practical, we describe a scalable interpolation architecture, and the first implementation of a complete trajectory "infrastructure" inside a full SPICE engine. The approach supports arbitrarily large training runs, automatically prunes redundant trajectory samples, supports limited hierarchy, enables incremental macromodel updates, and gives 3-10/spl times/ speedups for larger circuits.

/pdf/scalable-trajectory-methods-for-on-demand-analog-macromodel-10hsfcdj3m.pdf

Scalable trajectory methods for on-demand analog macromodel extraction

We have simulated the phase noise of a voltage controlled oscillator (VCO) using an RF circuit simulator, SpectreRF/sup TM/. This simulator uses a variation of the periodic noise analysis first proposed by Okumura, et al (1993). It computes the power spectral density of the noise as a function of frequency. By assuming that only white noise sources are present in the oscillator, it is possible to derive a simple relationship between the level of the phase noise and the jitter. This excludes flicker noise from consideration, however, since flicker noise is a low-frequency phenomenon, excluding it only affects the accuracy of the long-term jitter. We compared the jitter with measurement and found the error to be less than 2 dB. An AHDL model for the VCO that efficiently exhibits jitter in the time domain is included. The model was written in Verilog-A. This model can be used to determine the affect of VCO jitter on a larger system, such as a phase-locked loop (PLL).

https://www.researchgate.net/profile/Kimihiro-Ogawa/publication/3792461_VCO_jitter_simulation_and_its_comparison_with_measurement/links/55a4eae408aef604aa040ba8/VCO-jitter-simulation-and-its-comparison-with-measurement.pdf

K. Ogawa

Papers

VCO jitter simulation and its comparison with measurement