The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special, subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 /spl mu/m CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency. >

VLSI architectures for video compression-a survey

Improved spatial, temporal, and spatio-temporal noise reduction apparatus (10) and also apparatus for noise reduction in conjunction with one or several of the following functions: edge enhancement, spatial interpolation, magnification adjustment by spatial interpolation, and dynamic range compression (DRC). An embodiment of apparatus (10) comprises an image preprocessing unit (12), an estimation gain parameter computation unit (14) and a two-directional processor (16).

Apparatus and method for smoothing images

The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding. The advantage of this algorithm was completely utilized by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed 3-PE, 9-PE, and 27-PE architectures provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems. >

Parallel architectures for 3-step hierarchical search block-matching algorithm

A new approach to block-based motion estimation for video compression, called the genetic motion search (GMS) algorithm, is introduced. It makes use of a natural processing concept called genetic algorithm (GA). In contrast to existing fast algorithms, which rely on the assumption that the matching error decreases monotonically as the search point moves closer to the global optimum, the GMS algorithm is not fundamentally limited by this restriction. Experimental results demonstrate that GMS is more robust than other algorithms in locating the global optimum and is computationally simpler than the full search algorithm. GMS is also suitable for VLSI implementation because of its regularity and high architectural parallelism. >

Genetic motion search algorithm for video compression

It is increasingly important to structure signal processing algorithms and systems to allow for trading off between the accuracy of results and the utilization of resources in their implementation. In any particular context, there are typically a variety of heuristic approaches to managing these tradeoffs. One of the objectives of this paper is to suggest that there is the potential for developing a more formal approach, including utilizing current research in Computer Science on Approximate Processing and one of its central concepts, Incremental Refinement. Toward this end, we first summarize a number of ideas and approaches to approximate processing as currently being formulated in the computer science community. We then present four examples of signal processing algorithms/systems that are structured with these goals in mind. These examples may be viewed as partial inroads toward the ultimate objective of developing, within the context of signal processing design and implementation, a more general and rigorous framework for utilizing and expanding upon approximate processing concepts and methodologies.

Approximate Signal Processing

After many years of intensive deliberation, an international low-bit-rate video coding standard, known as CCITT (International Telegraph and Telephone Consultative Committee) Recommendation H.261, has been completed. The H.261 covers a wide range of bit rates at p*64 kbs, where p=1, 2, . . ., 30. A great deal of real-time signal processing power is required to compress an NTSC or other similar video signals to these rates for transport and to reconstruct the original signal back for display. In order to demonstrate the video quality of the newly established standard and the feasibility of a cost-effective VLSI solution, a real-time video codec based on H.261 has been constructed using ASICs (application specific integrated circuits). A single-board research prototype consisting of 11 ASICs with an aggregate signal processing power of approximately two billion operations per second is presented. >

K. Ohyama

Papers

An all-ASIC implementation of a low bit-rate video codec