In scaled technologies, performance improvements become increasingly limited by interconnect parasitics. The increased emphasis in the literature on low-resistance replacements for, or supplements to, polysilicon-gate technologies verifies the importance of parasitic limitations. Further, the role of the series source and drain resistance as well as contact resistance in limiting device performance has also been addressed by several authors. This role is further enhanced by the actual much more rapid increase in sheet resistivity with decreasing junction depth than previously assumed by other workers. In fact, it can be anticipated that metallurgical advances, such as silicides, will be required to compensate for the increased sheet resistance of source and drain diffusions. In the present work, a theoretical development of a transmission line model for a totally silicided diffusion is presented. Both the silicide and the diffusion sheet resistivities ρ S and ρ D , and the specific contact resistivity ρ c , are incorporated, unlike earlier models for contact holes only in which ρ S = 0. This model is applied to specific typical MOS structures, including single-section and three-section structures, to calculate the contact resistance contribution to total resistance. These results are used in conjunction with device equations addressing the device and circuit performance of small-geometry MOSFET's. Both n- and p-channel devices are considered as well as various scaling scenarios (constant field, constant voltage, etc.). These results show that for n-channel devices with a gate length of 1 µm, a-factor-of-two increase in circuit performance can be expected when using silicides. However, for p-channel devices, the expected performance gain as a result of using silicides is a factor of ten.

A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits

A novel two-dimensional (2D) process simulator has been developed which can handle local oxidation, implantation through arbitrary mask edges, nonplanar surfaces, and high concentration diffusion. Through coupling of 2D process and device simulators, the sensitivity of perimeter junction capacitance and breakdown voltage to variations in boron channel-stop implantation dose and local oxidation time has been simulated for a standard NMOS technology. Experimental results using test structures have confirmed the simulations. It is shown that simple power-law dependencies as a function of the process variables give good agreement with the data.

Process design using two-dimensional process and device simulators

In sealed technologies, performance improvements become increasingly tilted by interconnect parasitic. The increased emphasis in the literature on low-resistance replacements for, or supplements to, polysilicon-gate technologies verifies the importance of parasitic limitations. Further, the role of the series source and drain resistance as well as contact resistance in limiting device performance has also been addressed by several authors. This role is further enhanced by the actual much more rapid increase in sheet resistivity with decreasing junction depth than previously assumed by other workers. In fact, it can be anticipated that metallurgical advances, such as silicides, will be required to compensate for the increased sheet resistance of source and drain diffusions. In the present work, a theoretical development of a transmission line model for a totally silicided diffusion is presented. Both the silicide and the diffusion sheet resistivities/spl rho//sub S/ and /spl rho//sub D/, and the specific contact resistivity /spl rho//sub c/, are incorporated, unlike earlier models for contact holes only in which /spl rho//sub S/ =0. This model is applied to specific typical MOS structures, including single-section and three-section structures, to calculate the contact resistance contribution to total resistance. These results are used in conjunction with device equations addressing the device and circuit performance of small-geometry MOSFET's. Both n- and p-channel devices are considered as well as various scaling scenarios (constant field, constant voltage, etc.). These results show that for n-channel devices with a gate length of 1 /spl mu/m, a-factor-of two increase in circuit performance can be expected when using silicides. However, for p-channel devices, the expected performance gain as a result of using silicides is a factor of ten.

A Transmission Line Model for Silicided Diffusions: Impact on the Performance of VLSI Circuits

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.

On-chip capacitance measurement circuits in VSLI structures

Limitation of the coplanar technology to geometry miniaturization has been investigated. Two-dimensional nature of diffused line capacitance in a coplanar structure is investigated for the first time delineating importance of the sidewall capacitance with decreasing feature size of devices. The effects of field channel-stop ion implantation on the narrow-channel effect, the field MOS threshold voltage, and the junction breakdown voltage are also discussed.

Two-dimensional nature of diffused layers and certain limitations in scaling-down coplanar structure

Two dimensional nature of diffused line capacitance in the coplanar MOS LSI structure is investigated delineating importance of the side wall capacitance with decreasing feature size of devices. The effects of field channel stop ion implantation on the narrow channel effect, the field MOS threshold voltage and the junction breakdown voltage are also discussed toward optimization of coplanar process parameters.

K. Taniguchi

Papers

Two dimensional nature of diffused line capacitance in coplanar MOS structures