We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

With the evolution of wireless systems, more communication standards are being proposed while maintaining backward compatibility, therefore, there is an ever growing need for wideband multistandard receivers similar to software defined radio (SDR) receivers. For many years now, SDR or digitally reconfigurable radio research has been quite challenging with only a few reported practical prototypes with limited success. The basic demand of the SDR has been the need for a giant analog-to-digital converter (ADC) and a powerful enough digital signal processing (DSP) so that it serves as a universal radio platform receiving almost all radio standards and services. These demands are difficult to meet even in modern CMOS technologies leading to the necessity of highly flexible architectures compared to traditional receivers. To achieve this objective, digital intensive receiver architectures with passive structures are proposed. Radio frequency (RF) sampling receivers using time-interleaved (TI), RF sampling and discrete-time mixing also provide additional flexibility by employing discrete-time signal processing in analog domain. Owing to the oversampling ratio of up to 8 times in these receivers, high-performance complex frequency synthesizers are needed with stringent phase noise requirement. Moreover, the clocking schemes employed in TI RF sampling architectures result in additional timing jitter and mismatch offsets. These challenges are alleviated in a class of sampling receivers, called subsampling receivers, where the employed bandpass sampling principle results in less than the Nyquist sampling frequency. This leads to the less-complex and less power hungry frequency synthesizers. In this thesis, an intermediate solution to SDR receiver implementation called “Mini-SDR” architecture is proposed by exploiting the bandpass sampling concept. Based on the proposed Mini-SDR architecture, three CMOS radio frontends are proposed for standalone electronic attack (EA) transceiver system, dynamically reconfigurable multistandard subsampling (DRMS) radio receiver and a dual-band subsampling receiver for IEEE WLAN 802.11ac standard.

http://shodhganga.inflibnet.ac.in:8080/jspui/bitstream/10603/224424/1/01_title.pdf

Kale Ajinkya Umesh

Papers

Subsampling CMOS Frontends for Multistandard Reconfigurable RF Radios