Dictionary of Computing

A review on reversible quantum adders

The reversible logic has been gaining increased attention due to its characteristic feature of incurring low-power dissipation in digital circuits. It plays a major role in quantum computing. This paper suggests a novel 4 * 4 reversible gate called BKAS gate. One of the most interesting characteristic features of BKAS is that it can be functioned individually as a reversible full adder, as well as a full subtractor. This feature allows it to be used in the design of complex adder architectures with reduced garbage outputs, quantum cost, and ancilla input. The proposed BKAS gate is validated using a comparison with the prevailing reversible gates in the literature.

Quantum Cost Optimization of Reversible Adder/Subtractor Using a Novel Reversible Gate

Reversible logic is becoming more prominent logic for Power and Delay optimization. From last few years it has been incorporated in number of applications such as Bioinformatics, Quantum computing, DNA computing, Nanotechnology and low power VLSI. In Conventional digital circuits, the main cause of power dissipation is the disposal of bits of information while the logical operations are being carried out, So if these circuits are designed with reversible logic, the bit loss can be preserved. As 1-bit Full Adder is the elementary unit in almost all the digital circuits, So this paper gives the Comparative Analysis of 1 bit Full Adder circuit using reversible logic in order to find out the most efficient circuit in comparison to existing ones as in terms of Dynamic Power, Leakage Power, Area and Delay. All the circuits were designed with Verilog HDL and has been simulated Using NC-SIM. The RTL analysis was carried out with RTL compiler 14.01 by Cadence for Power, Area and Delay at 90nm and 45nm technology for both fast and slow library.

Comparative Analysis for Performance Evaluation of Full Adders Using Reversible Logic Gates

Multiplier is one among the essential hardware blocks in present-day communication and digital signal processing (DSP) systems. The primary advantage of Vedic multiplier is that delay increases slowly with the increase of input bits. Vedic multiplier has supreme advantage when compared with other multipliers over regularity of structures and gate delays. In this paper, the different designs of 8 * 8 bit Vedic multiplier are implemented with different adders, and these multipliers and adders are structured using suitable reversible logic gates, that is, Feynman gate, Peres gate, Toffoli gate, DPG gate and modified Fredkin gate. The different designs of Vedic multipliers designed with the help of different adders, that is, ripple carry adder, carry skip adder and carry select adder, and hence compared their implementation time as well as area required for the circuitry. This comparison will help designers to choose the preferable multiplier according to the application specific demands.

Design of Vedic Multiplier Using Reversible Logic Gates

Constant shrinkage in the device dimensions has resulted in very dense memory cells. The probability of occurrence of multiple bit errors is much higher in very dense memory cells. Conventional Error Correcting Codes (ECC) cannot correct multiple errors in memories even though many of these are capable of detecting multiple errors. This paper presents a novel decoding algorithm to detect and correct multiple errors in memory based on Matrix Codes. The algorithm used is such that it can correct a maximum of eleven errors in a 32-bit data and a maximum of nine errors in a 16-bit data. The proposed method can be used to improve the memory yield in presence of multiple-bit upsets. It can be applied for correcting burst errors wherein, a continuous sequence of data bits are affected when high energetic particles from external radiation strike memory, and cause soft errors. The proposed technique performs better than the previously known technique of error detection and correction using Matrix Codes.

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Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data

The reversible logic has been proved to play an important role in the low power VLSI design arena and the quantum dot cellular automata. The reversible circuits are building blocks of quantum computers since the operations involved in this are reversible. This paper proposes a novel 4*4 reversible gate called BKG gate. The most significant feature of the proposed gate is that it can be operated singly as a reversible full adder. This feature is proved to be helpful in designing complex adder architectures using lesser number of reversible gates and lower area. The validation is done using comparison with existing reversible gates.

Design of reversible adders using a novel reversible BKG gate

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A New Improved MCML Logic for DPA Resistant Circuits

An energy efficient and novel Charge Sharing Complementary Pass Transistor Adiabatic Logic (CSCPAL) operated by four phase power clock is proposed. It realizes low switching noise and incurs low leakage power. FinFETs are ideal devices for low power circuit design due to their enhanced properties of reduced short channel effects and lower leakage current. The circuits are designed using 32nm FinFET models and are simulated using Cadence® Virtuoso design tools. Efficiency of FinFET based CSCPAL is compared with FinFET based 2N2N2P, 2N2P and PFAL designs found in the literature. Energy consumption of CSCPAL Inverter/Buffer, AND and XOR sub modules used in the design of 8-bit Carry Lookahead Adder circuits have been compared with the 2N2P, 2N2N2P and PFAL based circuit counterparts. 8-bit CLA is taken as a benchmark circuit for validation of energy efficiency.

Kanchana Bhaaskaran V S

Papers

Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data

Design of reversible adders using a novel reversible BKG gate

A New Improved MCML Logic for DPA Resistant Circuits

Design and Analysis of FinFET Based CSCPAL Low Power Adder