This paper introduces a low-overhead hardware profiling architecture, called LEAP, that attains real-time cycle and energy profiles of an FPGA-based soft processor A novel technique is used to associate profiling data with specific functions in a way that is area- and power-efficient Results show that relative to a previously-published hardware profiler, our design uses up to 18× less area and 86× less energy LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated in this paper We also demonstrate the utility of LEAP in the context of hardware/software co-design of processor/accelerator FPGA-based systems

Low-cost hardware profiling of run-time and energy in FPGA embedded processors

Embedded Systems combine one or more processor cores with dedicated logic running on an ASIC or FPGA to meet design goals at reasonable cost. It is achieved by profiling the application with variety of aspects like performance, memory usage, cache hit versus cache miss, energy consumption, etc. Out of these, performance estimation is more important than others. With ever increasing system complexities, it becomes quite necessary to carry out performance estimation of embedded software implemented in a particular processor for fast design space exploration. Such profiled data also guides the designer how to partition the system for Hardware (HW) and Software (SW) environments. In this paper, we propose a classification for currently available Embedded Software Profiling Tools, and we present different academic and industrial approaches in this context. Based on these observations, it will be easy to identify such common principles and needs which are required for a true Software Profiling Tool for a particular application.

A Survey of Embedded Software Profiling Methodologies

The present application relates to an apparatus for detecting software interference and the method of operating thereof. A processor and at least one shared resource form a computing shell to execute a first, functional safety critical application and at least one second application in time-shared operation. One or more performance counters are provided to adjust a counter value in response to a performance related event. A reference value storage stores one or more threshold values, each of which is associated with one of the performance counters. A comparator receives the performance counter values, compares the performance counter values with the respective threshold values and generates at least one comparison signal in response to results of the comparisons. An interference indication generator receives the at least one comparison signal and generates at least one interference indication in response to the at least one received comparison signal.

Methods and apparatus for detecting software inteference

Security is the weighty part in wireless communication system, where more randomization in secret keys increases the security as well as complexity of the cryptography algorithms. The AES is used to protect data in cryptography. It is a symmetric block cipher in which encryption and decryption is takes place. For the performance AES algorithm is discussion from its starting publication. The propose method is to design AES algorithm by using Xilinx ISE 13.1. The simulated result shows the different parameters such as power and time of AES algorithm.

Design OF Advanced Encryption Standard Algorithm Using Xilinx Project Navigator, ISE 13.1

Evolutionary algorithms are very common techniques used in computational intelligence and robotics field applications. Some algorithms need a large amount of memory and processing power, making them difficult to implement into embedded systems. In this work a profile-based approach is proposed and applied in an evolutionary algorithm with some characteristics that allow it’s use on embedded systems and robotics: the micro-GA. The main goal is to implement a new hardware-software co-design architecture for this genetic algorithm with better execution time than algorithms implemented in software (using general purpose hardware solutions). The presented results show a comparison between different code sign implementations and discussion about new architecture advantages.

HW/SW Co-design Architecture for Evolutionary Robotics

Embedded systems are a mixture of software running on a microprocessor and application-specific hardware. Hardware/Software co-design requires an appropriate profiler to detect the functions that contribute to a large percentage of program execution. Software based profiling tools, such as the well-known GNU gprof profiler, integrates an extra code with the software program to be profiled causing a significant performance overhead. To address this issue, this paper proposes a software profiler called AddressTracer. This profiler is an adaptation of a non-intrusive, real time profiler called SnoopP. The AddressTracer is accurately able to evaluate the performance matrices of any specific software function. A software benchmark, Secure Hash Algorithm (SHA), is profiled using AddressTracer and other software profiling tools, Airwolf, and GNU software profiling tool (gprof), for a quantitative comparison and their performance overhead are studied. The achieved results show that AddressTracer provides accurate profiling results with no performance overhead. Airwolf causes a very low remarkable performance overhead compared with that incurred by gprof.

FPGA-based software profiler for Hardware/Software co-design

Embedded systems are a mixture of software running on a microprocessor and application-specific hardware. There are many co-design methodologies that are used to design embedded systems. One of them is Hardware/Software co-design methodology which requires an appropriate profiler to detect the software portions that contribute to a large percentage of program execution and cause performance bottleneck. Detecting these software portions improves the system efficiency where these portions are either reprogrammed to eliminate the performance bottleneck or moved to the hardware domain gaining the advantages of this domain. There are profiling tools used to profile software programs such as GNU Gprof profiler. GNU Gprof integrates an extra code with the software program to be profiled causing inaccurate results and a significant execution time overhead. To address these issues, this paper proposes a software profiler called AddressTracer that is accurately able to evaluate performance matrices of any specific software portion. A set of benchmarks, Dijkstra, Secure Hash Algorithm, and Bitcount are profiled using AddressTracer, Airwolf and GNU software profiling tool (Gprof), for a quantitative comparison. The achieved results show that AddressTracer gives accurate profiling results compared to Gprof and Airwolf profilers. AddressTracer provides up to 50.15% improvement in accuracy of profiling software compared to Gprof and 6.89% compared to Airwolf. Furthermore, AddressTracer is a non-intrusive profiler which does not cause any performance overhead.

Kareem Ezz El-Deen

Papers

FPGA-based software profiler for Hardware/Software co-design

Real-Time Software Profiler for Embedded Systems