A unified algorithm for elementary functions

Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation. But, we do not find any optimized coordinate rotation digital computer (CORDIC) design for vector-rotation through specific angles. Therefore, in this paper, we present optimization schemes and CORDIC circuits for fixed and known rotations with different levels of accuracy. For reducing the area- and time-complexities, we have proposed a hardwired pre-shifting scheme in barrel-shifters of the proposed circuits. Two dedicated CORDIC cells are proposed for the fixed-angle rotations. In one of those cells, micro-rotations and scaling are interleaved, and in the other they are implemented in two separate stages. Pipelined schemes are suggested further for cascading dedicated single-rotation units and bi-rotation CORDIC units for high-throughput and reduced latency implementations. We have obtained the optimized set of micro-rotations for fixed and known angles. The optimized scale-factors are also derived and dedicated shift-add circuits are designed to implement the scaling. The fixed-point mean-squared-error of the proposed CORDIC circuit is analyzed statistically, and strategies for reducing the error are given. We have synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-nm library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed and known angles of rotation. We find similar results of synthesis for different Xilinx field-programmable gate-array platforms.

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CORDIC Designs for Fixed Angle of Rotation.

This paper presents a designing scheme of high-speed real-time serial pipelined Fast Fourier Transform (FFT) processor on FPGA which is based on Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm will reduce the hardware complexity compared to the direct implementation of the butterflies using complex multipliers. Moreover, the design uses the butterflies of the radix-2 Decimation-In-Time (DIT) algorithm, the dual-port RAM and the pipelined structure, which will sufficiently increase the performances of the FFT processor. The simulation results show that compared with the same type of real-time FFT processor, the scheme presented in this paper reduces the hardware resource requirements of Adaptive Look-up Tables (ALUTs) and increase the Signal Noise Ratio (SNR) by about 25dB.

CORDIC-based FFT real-time processing design and FPGA implementation

A wideband digital transmitting beamformer based on linear frequency modulation (LFM) signals is presented in this study. The wideband beamformer is realised as a combination of direct digital synthesisers and fractional delay (FD) filters in polyphase structure. By using coordinate rotation digital computer algorithm, high intermediate frequency wideband LFM signal is generated and phase compensation for beamforming is accomplished in field programmable gate array. The impact of different number of quantisation bits on signal generation is analysed. The results of waveform generation and FD filter design are given. At last, the transmitting beam pattern is simulated.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-spr.2016.0114

Implementation of wideband digital transmitting beamformer based on LFM waveforms

This paper presents a novel Fourier-domain optical coherence tomography (FDOCT) imaging processor capable of performing all image formation operations, including dc removal, resampling, real-valued fast Fourier transform (RFFT), and display rendering. Optimizing an RFFT unit through complex-valued FFT computation makes it possible to reduce the clock rate required for the RFFT and post-RFFT units by half, thereby enhancing energy efficiency. A novel resource-sharing scheme further enables calibration (i.e., calculation of resampling indices) awareness checking with minimal area overhead. This makes the proposed FDOCT imaging processor ideally suited to portable OCT application. A test chip operating at dual 80/40 MHz was designed using the Taiwan Semiconductor Manufacturing Company 0.18- $\mu \text{m}$ technology. In postlayout simulation of FDOCT imaging mode, the test chip was shown to consume only 283.6 mW, which represents a power saving of 29% compared to an equivalent design without optimization. The proposed design was also verified at the system level using a field programmable gate arrays (FPGA) platform. In evaluation experiments, we could achieve 78-KHz A-line scan and 30-fps $512\times 1000$ OCT image display. The developed FPGA design also supports calibration awareness check using modest hardware resources.

Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor

Fast Fourier Transform (FFT) is one of the basic building blocks in signal processing and communications systems. The butterflies-based structure of the FFT is the main reason for the reduced number of arithmetic operations required to implement the transform. From implementation point of view, the complex rotations used in butterflies can be implemented by using COordinate Rotation DIgital Computer (CORDIC). This implementation strategy reduces the hardware complexity compared to the direct implementation of the butterflies using complex multipliers. In this paper, we introduce a restructure of the butterflies of the radix-2 FFT to be more CORDIC friendly. This algorithm-level modification of the FFT is friendly towards all CORDIC types, including those introducing non-fixed gain. Compared with the conventional radix-2 FFT algorithm, the proposed algorithm introduces a substantial increase in performance. For example, it achieves superior signal to quantization noise ratio (SQNR), with around 14 dB gain for 8 to 1024 points FFT. In addition, in pipeline architectures the modification leads to an improvement in latency or a reduction in the total area, with an improvement in either of 38% for 1024 points FFT.

A CORDIC-friendly FFT architecture

A new security processor has been recently proposed which accepts the assembly code for arbitrary security algorithms, and executes it efficiently, thanks to its use of a data-flow architecture that distributes arithmetic and logical Function Units FUs over a number of Execution Regions ERs. In this paper, a structured approach is presented to determine the optimal solution of the processor architecture in which one seeks the best combination of the number of ERs and the assignment of 27 FUs to these ERs. In order to cover the huge design space, a structured approach has been adopted which is based on the use of a powerful software simulator and the customization of the Genetic Algorithm NSGA-II for efficient optimization. Numerical results have been obtained and the optimal security processor architecture has been deduced by considering the AES Encryption algorithm as the reference assembly code.

Structured Design Approach for an Optimal Programmable Synchronous Security Processor

Optimization of a novel programmable data-flow crypto processor using NSGA-II algorithm.

The architecture of a recently proposed Globally Asynchronous Locally Synchronous (GALS) processor dedicated to security programs is considered. Operations are performed using a number of Functional Units (FUs) grouped into a number of Execution Regions (ERs) working with independent clocks. The selection of the number of ERs as well as the distribution of the FUs among regions is approached as a multi-objective optimization problem with the objective functions selected as area, delay, and energy. This problem is solved using the NSGA-II algorithm. The obtained solutions are compared with those obtained in the case of operating all regions with the same clock. It is shown that for the case of AES encryption and with high communication delay overheads the synchronous case achieves a better performance. However, by reducing these overheads and speeding up the instruction region, execution delay with asynchronous operation can be reduced to 56% of the delay in the synchronous case.

Karim Osama

Papers

A CORDIC-friendly FFT architecture

Structured Design Approach for an Optimal Programmable Synchronous Security Processor

Optimization of a novel programmable data-flow crypto processor using NSGA-II algorithm.

Multi-objective genetic algorithm-based optimization of an asynchronous data-flow security processor