Kaushik Datta

TL;DR: This work explores multicore stencil (nearest-neighbor) computations --- a class of algorithms at the heart of many structured grid codes, including PDF solvers, and develops a number of effective optimization strategies, and builds an auto-tuning environment that searches over these strategies to minimize runtime, while maximizing performance portability.

TL;DR: Results demonstrate that recent trends in memory system organization have reduced the eficacy of traditional cache- blocking optimizations, and represent one of the most extensive analyses of stencil optimizations and performance modeling to date.

TL;DR: Two related projects, the Titanium and UPC projects, combine compiler, runtime, and application efforts to demonstrate some of the performance and productivity advantages to these languages.

TL;DR: Several optimizations on both the conventional cache-based memory systems of the Itanium 2, Opteron, and Power5, as well as the heterogeneous multicore design of the Cell processor are examined, including both an implicit cache oblivious approach and a cache-aware algorithm blocked to match the cache structure.

TL;DR: The opportunity for using machine learning in multicore autotuning is even more promising than the successes to date in the systems literature, and state-of-the-art machine learning techniques are applied to explore this space more intelligently.