An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Integrated chip package structure using organic substrate and method of manufacturing the same

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations

Self-aligned contacts

To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Semiconductor dicing and assembling method

An electroconductive or insulative film 100 is formed over a surface of a semiconductor substrate 1. A first photoresist 101 is coated over the film 100, and is then patterned. The film 100 is selectively removed by etching to expose a given area of the substrate 1. Subsequently an impurity of the first conductivity type is doped into the exposed area to form a first impurity region. After removing the first photoresist 101, a second photoresist 103 is coated entirely over the film 100, and is then patterned. Subsequently, the film 100 is selectively removed from another given area by etching. Another impurity of the second conductivity type is doped into the exposed area to form a second impurity region 104. Only the two steps of the photoresist patterning are carried out to form the impurity regions of the different conductivity types, thereby reducing production cost of the semiconductor device. The impurity can be doped by ion implantation while covering the film 100 with the photoresist, thereby facilitating micronization and integration of the semiconductor device.

Method of producing low and high voltage MOSFETs with reduced masking steps

In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal. Thus, the power management semiconductor device or analog semiconductor device, which is advantageous in terms of cost, manufacturing period and element performance in comparison with the conventional CMOS with an N+polycrystalline silicon gate single polarity or the same polarity gate CMOS in which a channel and a gate electrode have the same polarity, can be realized.

Complementary MOS semiconductor device

A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut. This may be accomplished, for example, by measuring a first current which flows in the drain terminal while applying a first voltage to the gate terminal and a second voltage to the drain terminal relative to an electric potential of the source terminal, then measuring a second current which flows in the drain terminal while applying a third voltage to the gate terminal and the second voltage to the drain terminal relative to an electric potential of the source terminal. In order to achieve the desired current characteristic, selected conductive lines between coupled drains or between coupled sources are then cut.

Current regulating semiconductor integrated circuit device and fabrication method of the same

A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.

Kazutoshi Ishii

Papers

Semiconductor dicing and assembling method

Method of producing low and high voltage MOSFETs with reduced masking steps

Complementary MOS semiconductor device

Current regulating semiconductor integrated circuit device and fabrication method of the same

Semiconductor device and method of fabricating the same