A wide variety of semiconductor devices are used in wireless power amplifiers. The RF performance and other attributes of cellphone RF power amplifiers using Si and GaAs based technologies are reviewed and compared.

RF power amplifiers for wireless communications

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

A system for transmitting digital programming includes a program source providing digital information, circuitry for modulating the digital information onto a visual carrier modulated with analog television programming, and a visual transmitter coupled to the modulating circuitry. Using a phase modulation method, the system phase modulates the digital information onto a visual carrier, reduces the baseband frequencies of the phase modulated visual carrier, and amplitude modulates the phase-modulated video carrier onto a video signal. The amplified and encoded video signal are combined with an amplified sound signal and transmitted. Using an additive method, the system modulates the sidebands of the video carrier with the digital information and amplitude modulates the video signal onto the video carrier. The data-modulated sidebands are phase-shifted such that they will be in quadrature with the amplitude-modulated video signal. The system combines the amplitude-modulated video carrier and the data-modulated quadrature sidebands. With a blended multiplicative/additive method, the system provides phase modulation and quadrature sideband addition to provide an optimized result.

Expanded information capacity for existing communication transmission systems

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

A duplexer circuit apparatus includes (a) a transmission arm circuit including a first switching circuit which is connected between a transmitter and an antenna, is turned on during transmission, and is turned off during reception, and (b) a reception arm circuit including a second switching circuit which is connected between a receiver and the antenna, is turned off during transmission, and is turned on during reception. In the duplexer circuit apparatus, either the transmitter or the receiver is selectively connected to the antenna, and the transmission arm circuit further includes a cascode amplifier, and an impedance matching inductor connected between the cascode amplifier and the antenna. In this case, the cascode amplifier may be replaced by a source-grounded amplifier constituted by only the FET.

Duplexer circuit apparatus provided with amplifier and impedance matching inductor

A power amplifier including an amplifier stage including a heterojunction bipolar transistor for signal amplification having a base electrode connected to an RF signal input terminal, and a grounded emitter electrode; and a bias circuit including a silicon bipolar transistor having a base electrode connected to a power supply terminal, and a terminal from which a current amplified in response to a base current is output, which terminal is connected to the base electrode of the heterojunction bipolar transistor stage. In this power amplifier, since the voltage required for operating the bias circuit is reduced, a power amplifier capable of operating at a low voltage is realized.

Power amplifier incorporating heterojunction and silicon bipolar transistors

Disclosed is an output overvoltage protection circuit for a power amplifier having a plurality of stages, which comprises a monitor circuit for monitoring an output overvoltage of an output transistor in the final stage of the power amplifier and allowing a current to flow therethrough in response to the monitored output overvoltage, and a current mirror circuit for supplying a current proportional to the current from the monitor circuit in such a manner that the base bias of the first-stage transistor of the power amplifier is reduced in response to the current supplied from the current mirror circuit, to reduce the output of the final-stage output transistor.

Output overvoltage protection circuit for power amplifier

This paper describes new single-chip RF front-end GaAs MMIC for 1.9 GHz Japanese PHS handheld terminals. The IC consists of a high power amplifier, a T/R switch, a low noise amplifier, a newly developed low distortion cascode FET mixer and a negative voltage generator for FET gate bias voltage. The IC has high performance as an RF front-end for PHS terminals.

A 1.9 GHz single-chip RF front-end GaAs MMIC with low-distortion cascode FET mixer for personal handy-phone system terminals

This paper describes a 3.5-V operation HBT MMIC power amplifier module for use in GSM/EDGE dual-mode, 900/1800/1900-MHz triple band handset applications. With diode switches and a band select switch built on the MMIC, the module delivers a P/sub out/ of 35.5 dBm and a PAE of about 50% for GSM900, a 33.4-dBm P/sub out/ and a 45% PAE for GSM1800/1900. While satisfying an error vector magnitude (EVM) of less than 4% and a receive-band noise power of less than -83 dBm/100 kHz, the module also delivers a 29.5 dBm P/sub out/ and a PAE of over 25% for EDGE900, a 28.5 dBm P/sub out/ and a PAE of over 25% for EDGE1800/1900.

Kazuya Yamamoto

Papers

Duplexer circuit apparatus provided with amplifier and impedance matching inductor

Power amplifier incorporating heterojunction and silicon bipolar transistors

Output overvoltage protection circuit for power amplifier

A 1.9 GHz single-chip RF front-end GaAs MMIC with low-distortion cascode FET mixer for personal handy-phone system terminals

A GSM/EDGE dual-mode, 900/1800/1900-MHz triple-band HBT MMIC power amplifier module