A system and method for transferring data in a library storage system. The library storage system comprises a management server including a storage policy. A media agent is connected to the management server. A plurality of storage media and a data source are connected to the media agent. The data source is divided into at least a first and a second portion of data. The portions of data are transferred from the data source to a first and second primary storage medium using a first and a second data stream respectively. The media agent then causes the first and second portion of data to be transferred from the first and second storage medium to a third auxiliary storage medium using a third combined data stream. Auxiliary copying is performed in chunks and multiple streams are copied in parallel.

Combined stream auxiliary copy system and method

A method for controlling coherence of data elements sharable among a plurality of independently-operating CPCs (central processing complexes) in a multi-system complex (called a parallel sysplex) which contains sysplex DASDds (direct access storage devices) and a high-speed SES (shared electronic storage) facility. Sysplex shared data elements are stored in the sysplex DASD under a unique sysplex data element name, which is used for sysplex coherence control. Any CPC may copy any sysplex data element into a local cache buffers (LCB) in the CPC's main storage, where it has an associated sysplex validity bit. The copying CPC executes a sysplex coherence registration command which requests a SES processor to verify that the data element name already exists in the SES cache, and to store the name of the data element in a SES cache entry if found in the SES cache. Importantly, the registration command communicates to SES the CPC location of the validity bit for the LCB containing that data element copy. Each time another copy of the data element is stored in any CPC LCB, a registration command is executed to store the location of that copy's CPC validity bit into a local cache register (LCR) associated with its data element name. In this manner, each LCR accumulates all CPC locations for all LCB validity bits for all valid copies of the associated data element in the sysplex -- for maintaining data coherency throughout the sysplex.

Sysplex shared data coherency method

Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system

A hardware-accelerated recirculating programmable texture blender/shader arrangement circulates computed color and alpha data over multiple texture blending/shading cycles (stages) to provide multi-texturing and other effects. Up to sixteen independently programmable consecutive stages, forming a chain of blending operations, are supported for applying multiple textures to a single object in a single rendering pass.

Recirculating shade tree blender for a graphics system

A microprocessor controlled digital engine analyzer receives analog input signals from an engine being analyzed, engine parameter data entered via a keyboard, and function data, selecting one of several operating modes for the analyzer and which information is to be displayed, entered via the keyboard, and displays on a CRT screen the selected information such as cylinder firing order, RPM, Dwell, KV and DC volts, alphanumerically, information such as primary and secondary ignition and voltage, alternator and fuel injector information through the use of continuous waveform patterns, and additional information pertaining to Dwell, KV and Cylinder Shorting through the use of bar graphs. The waveform pattern data derived from the analog input signals is stored in a dual bank waveform memory and read out for display on the CRT screen under hardware control, and address data representing alphanumeric data and screen formats for the various operating modes to be displayed is stored in a dual bank display memory for application to a character generator, a bank switching arrangement being used for both the waveform memory and the display memory to enable the banks of each memory to be alternately written to and read from. A main microprocessor receives and processes analog input signals, other than the waveform pattern signals, and a display microprocessor receives numerical data from the main microprocessor and causes display of the numerical data on the CRT screen.

Digital engine analyzer

A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

Keeley James W

Papers

Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization