A synchronous semiconductor memory device including a memory cell array and a plurality of input receivers to sample address information synchronously with respect to a clock signal. The address information includes a row address and a column address. The memory device further includes a plurality of sense amplifiers to sense data from a row of the memory cell array, the row of the memory cell array being identified by the row address. Furthermore, the memory device includes a plurality of column decoders coupled to the plurality of sense amplifiers to access, based on the column address, a plurality of data bits of the data sensed by the plurality of sense amplifiers. In addition, the memory device includes a plurality of output drivers to output the plurality of data bits, the plurality of output drivers outputs a first portion of the plurality of data bits synchronously with respect to a rising edge transition of the first clock signal, and the plurality of output drivers outputs a second portion of the plurality of data bits synchronously with respect to a falling edge transition of the first clock signal.

Synchronous memory device

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Memory device having a programmable register

A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing block size information to the memory device, synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes issuing a first read request to the memory device, wherein the memory device receives the first read request synchronously with respect to a transition of the external clock signal.

Memory device having a variable data output length

A synchronous integrated circuit device including a clock receiver to receive an external clock signal and a plurality of output drivers to output data. A first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal. A second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal. In addition, the integrated circuit device includes a delay locked loop, coupled to the plurality of output drivers and the clock receiver, to synchronize the output of the first and second portions of the data with the external clock signal.

Integrated circuit device having double data rate capability

A memory module including an integrated circuit is disclosed. In one particular exemplary embodiment, the memory module may comprise a plurality of memory devices and an integrated circuit device that is coupled to the plurality of memory devices. The integrated circuit device includes a first circuit to receive control information specifying a write operation, and address information specifying a memory location corresponding to the write operation, wherein the memory location is in a first memory device of the plurality of memory devices, and wherein the control information and the address information are received in a multiplexed format. The integrated circuit device also includes a second circuit, including a plurality of output drivers, to output data after a first number of clock cycles of an external clock signal transpire, wherein the data is to be written to the first memory device during the write operation.

Memory module including an integrated circuit device

A flip-flop stores input data on both the leading and trailing edges of a clock pulse. The flip-flop includes a data path responsive to the leading edge of a clock pulse and a second data path responsive to the trailing edge of a clock pulse, thereby allowing data to be stored on both the leading edge and the trailing edge of a clock pulse.

Kelly B. Cameron

Papers

Flip-flop for storing data on both leading and trailing edges of clock signal