As negative-MOSFET (NMOSFET) size and voltage are scaled down, the electron-energy distribution becomes increasingly dependent only on the applied bias, because of quasi-ballistic transport over the high-field region. A new paradigm, or underlying concept, of NMOSFET hot-carrier behavior is proposed here, in which the fundamental "driving force" is available energy, rather than peak lateral electric field, as it is in the lucky electron model (LEM). The new prediction of the energy-driven paradigm is that the bias dependence of the impact-ionization (II) rate and hot-carrier lifetime is, to the first order, given by the energy dependences of the II scattering rate S/sub II/(E) and an effective interface state generation (ISG) cross section S/sub IT/(E), whereas, under the LEM, these bias dependences are determined by the number of electrons with energy above the II and ISG "threshold energies." This approach allows an experimental determination of S/sub IT/.

The energy-driven paradigm of NMOSFET hot-carrier effects

Hot-carrier and oxide reliability of CMOS FinFETs with 21 nm-thick gate-SiO/sub 2/ were investigated It was found that hot-carrier immunity improves as the fin width (body thickness) decreases, which facilitates gate-length scaling, while it is degraded at elevated temperature due to the self-heating effect High values of Q/sub BD/ are achieved for devices with very small gate area A post-fin-etch hydrogen anneal is helpful for improving hot-carrier immunity and Q/sub BD/

Reliability study of CMOS FinFETs

A simple noninvasive optical technique for characterization of self-heating dynamics in advanced metal-oxide-semiconductor field-effect transistors is reported for the first time. The technique uses time-resolved photon emission microscopy to measure the temperature-dependent luminescence of off-state leakage current. It measures the temperature of the device channel, independent of surrounding materials or interconnects. The technique has been used to measure, for the first time, self-heating dynamics in silicon-on-insulator and strained-silicon n-field-effect transistors.

Time-resolved measurements of self-heating in SOI and strained-silicon MOSFETs using photon emission microscopy

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.

Device level Self-Heating (SH) is becoming a limiting factor during traditional DC Hot Carrier stresses in bulk and SOI technologies. Consideration is given to device layout and design for Self-Heating minimization during HCI stress in SOI technologies, the effect of SH on activation energy (Ea) and the SH induced enhancement to degradation. Applying a methodology for SH temperature correction of extracted device lifetime, correlation is established between DC device level stress and AC device stress using a specially designed ring oscillator.

Self-heating and its implications on hot carrier reliability evaluations

The authors present a thermal activation perspective for direct assessment of the low voltage impact ionization in deep-submicrometer MOSFETs. A comparison of the experimentally determined activation energy and a simple theoretical model is used to demonstrate the underlying mechanism responsible for impact ionization at low drain bias. The study indicates that the main driving force of impact ionization changes from the electric field to the lattice temperature with power-supply scaling below 1.2 V. This transition of driving force results in a linear relationship between log(I/sub SUB//I/sub D/) and V/sub D/ at sub-bandgap drain bias, as predicted by the proposed thermally-assisted impact ionization model.

A thermal activation view of low voltage impact ionization in MOSFETs

This letter reports an enhanced substrate current at high gate bias in SOI MOSFETs. A comparison between coprocessed bulk and partially depleted SOI MOSFETs is used to present the enhancement unique to SOI devices and demonstrate the underlying mechanism. Other than electric field, a new source for carrier heating in the channel, i.e., self-lattice heating, is found to be responsible for the excess substrate current observed. The impact of this phenomenon on SOI device lifetime prediction and compact modeling under dynamic operating conditions typical of digital circuit operation is described. This SOI-specific enhancement must be considered in one-to-one comparisons between bulk and SOI MOSFETs regarding hot-carrier effects.

Enhanced substrate current in SOI MOSFETs

This work demonstrates that excess hot-carrier currents in SOI MOSFETs are caused by self-heating. Self-heating-free I/sub SUB/ data should be used for dynamic lifetime extrapolation due to long thermal time constant. The underlying mechanism, increased impact ionization with temperature at low drain bias, is studied experimentally from the angle of thermal activation energy. Our study indicates that the driving force of impact ionization transitions from the electric field to the lattice temperature with power-supply scaling below 1.2 V.

Excess hot-carrier currents in SOI MOSFETs and its implications

A Co salicide process using TiN-cap metal reduces the sheet resistance in narow gate, source and drain regions. However, the detailed mechanism of the cap metal has not been well explained. We investigated various Co salicide processes and clarified the effect of the cap-metal. We found that the Co salicide process without cap-metal was very sensitive to the oxygen, even in very small concentration in the annealing chamber. We found that the cap-metal did not work as a promoter of the silicide reaction through metal stess, but did work mainly as a barrier to oxidation. Using these findings we demonstrated a low sheet resistance in narrow regions down to 0.075 pm with several methods.

Ken-ichi Goto

Papers

A thermal activation view of low voltage impact ionization in MOSFETs

Enhanced substrate current in SOI MOSFETs

Excess hot-carrier currents in SOI MOSFETs and its implications

Effect of Cap-Metals on Co Salicide Process