An electronic still camera comprising a lens, shutter, and exposure control system, a focus and range control circuit, a solid state imaging device incorporating a Charge Coupled Device (CCD) through which an image is focused, a digital control unit through which timing and control of an image for electronic processing is accomplished, an Analog-to-Digital (A/D) converter circuit to convert the analog picture signals into their digital equivalents, a pixel buffer for collecting a complete row of an image's digital equivalent, a frame buffer for collecting all rows of an image's digital equivalent, and a selectively adjustable digital image compression and decompression algorithm that compresses the size of a digital image and selectively formats the compressed digital image to a compatible format for either the IBM Personal Computer and related architectures or the Apple Macintosh PC architecture as selected by the operator so that the digital image can be directly read into most word processing, desktop publishing, and data base software packages including means for executing the appropriate selected decompression algorithm; and a memory input/output interface that provides both temporary storage of the digital image and controls the transmission and interface with a standard Personal Computer (PC) memory storage device such as a digital diskette. The digital diskette is removably inserted into the housing of the camera prior to use in recording digital image data.

Electronic still video camera with direct personal computer (pc) compatible digital format output

A video display terminal capable of operating with a graphical user interface such as Windows provides windowing functionality to permit use of popular applications programs resident on a server, without requiring more than application data to be transmitted from the server, and keyboard and mouse information to be transmitted from a terminal to the server. A terminal for communicating with a server includes a network interface for communicating with a server and a processor coupled to the network interface for operating with the network interface and for accessing a windows application resident on the server without executing locally the windows application resident on the server. The processor provides windowing functionality to permit use of a windows application resident on the server without requiring more than windowing information of the windows application to be transmitted from the server, wherein the windowing information includes application data. The terminal further includes one or more memories coupled to the processor, wherein the total amount of the one or more memories in the terminal is less than the total amount of one or more memories in the server. The terminal does not include a hard disk, and the terminal is for providing an appearance that is essentially the same as an appearance provided by a personal computer.

Method and apparatus for display of windowing application programs on a terminal

A digital signal processor (DSP) provides an improvement in the interfacing and sharing of external memory devices. Specifically, the digital signal processor is provided with a parallel interface for communicating with external memory devices, a chip select decoder located on-chip for selectably enabling external memory devices, and a wait status controller for holding processor operation until the selected memory device is ready. The memory architecture is configurable for internal or external wait state generation and memory sharing with other DSPs so that a plurality of varying speed memory devices may be accessed. The chip select decoder includes a programmable register for storing a mode configuration word for defining a plurality of external memory configurations.

Digital signal processor with on-chip select decoder and wait state generator

A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Devices and method for generating and using systems, software waitstates on address boundaries in data processing

An interface for a high-performance graphics adapter is provided. In a computer system which includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application computer program running on the host processor utilizes a graphics operating system, such as an Extended Graphics Array Input/Output System (XGA BIOS) to write graphics data in XGA format to the memory. A totally awesome controller translates memory addresses generated by the XGA BIOS (and hence the host processor) into memory addresses recognized by the coprocessor. One or more graphics controllers selectively swap pixel data between Intel order and Motorola order and store the graphics data, into an XGA video-random-access memory (RAM) buffer. A back-end gate array parallel-serial converts input display data in units of designated pixel data, and the graphics data is displayed on a CRT.

External interface for a high performance graphics adapter allowing for graphics compatibility

An image processing apparatus designed to interface with different monitors which processes image data read from a video random access memory (VRAM) so as to display an image corresponding to the image data on a screen of a display unit under a control of a central processing unit (CPU). The image processing apparatus at least provides a plurality of registers and a memory for storing several kinds of reference data for several kinds of predetermined modes. When one mode is selected from the predetermined modes, one of a color display and a monochromatic display is selectively performed on a screen of one of a color monitor and a monochromatic monitor or a screen of one of moniters each having different standard. The reference data corresponding to the selected mode are read from the memory and stored in the registers. When the selected mode is changed, reference data stored in requisite registers selected by newly selected mode are automatically rewritten by the reference data selected by the newly selected mode without exchanging programs of the CPU.

Image processing system interfacing with different monitors

An image processing apparatus processes image data stored in a memory to thereby display an image on a display screen of a display unit under a control of a central processing unit (CPU). In one aspect of the invention, source data read from a source area of the memory are subjected to a rotation process and a logical operation and then converted to transfer data which will be written in a destination area of the memory by every word. In addition, first and last words within one line on the display screen are masked in accordance with predetermined first and second mask data. In another aspect of the invention, one of a wait mode and a not-wait mode is selected by wait control data outputted from the CPU. In the wait mode, the CPU is subjected to a wait state even in a memory read cycle. In the not-wait mode, the CPU is not subjected to the wait state normally in the memory read cycle. However, the CPU is subjected to the wait state in the not-wait mode while a reading operation of the memory has not been completed.

Apparatus for processing image data for displaying an image on a display unit

PURPOSE:To directly take a synchronization according to a synchronizing signal extracted from an external video signal by presetting a counter for instructing horizontal and vertical positions to a preset value when an external synchronizing signal is supplied. CONSTITUTION:A picture processor 1 reads picture data (character code) in a VRAM3 under the control of a CPU2 and displays on a CRT display deice 5 based on the read data. the VRAM3 is suitably made access from the picture processor 1 or the CPU2 according to the switching processing of a multiplexer 4. A character generator 7 outputs dot data constituting a character pattern based on the character code supplied from the VRAM3 and a raster address RA supplied from the picture processor 1. In the picture processor 1, the counter for instructing the horizontal and vertical positions is disposed, and preset by the external synchronizing signal to decide the raster address.

Synchronizing method for picture processor

PURPOSE: To prevent malfunction of each part of the circuit used for the titled apparatus by using a clock supplied to the 1st input terminal normally as a master clock and using a substitution clock as the master clock in switching the frequency of the master clock. CONSTITUTION: A dot clock pulse DCK and a substitution clock pulse FCK are supplied to input terminals A, B of a selector 20 via terminals T 1 , T 2 . In switching the frequency of the clock DCK supplied to the 1st input terminal B, the clock FCK is used with switching. While the clock FCK is used as the master clock, the clock DCK supplied to the 1st input terminal B is switched and then the clock DCK supplied to the 1st input terminal B is outputted as the master clock. Thus, in switching the frequency of the master clock. The level period of the active side of the master clock is not decreased and the malfunction of each part of the circuit is prevented. COPYRIGHT: (C)1988,JPO&Japio

Kenji Iwamoto

Papers

Image processing system interfacing with different monitors

Apparatus for processing image data for displaying an image on a display unit

Synchronizing method for picture processor

Method and apparatus for changing synchronizing clock