When an energetic ion traverses a polymer medium, it loses its energy by electronic and nuclear processes. In the past, considerable research efforts have been devoted to understand the effects of the electronic and nuclear processes in materials. There have been, however, some conflicting reports regarding the roles of electronic and nuclear stopping in producing property changes in polymeric materials, namely the magnitude of cross-linking and scission. A consensus derived from the work conducted at ORNL indicates that electronic stopping is largely responsible for cross-linking and nuclear stopping for scission, although both processes can cause cross-linking as well as scission. The most important parameter for cross-linking is found to be the energy deposited per unit ion path length or linear energy transfer (LET). The mechanisms involved with property changes are discussed by clarifying the concepts of nuclear and electronic stopping, LET, tracks, and spurs. Experimental evidence to support the views are presented. Also addressed are specific property changes induced by ion-beams, which may be of use for industrial applications.

Ion-beam modification of polymeric materials – fundamental principles and applications

The present invention is directed to methods for patterning a substrate by imprint lithography. Imprint lithography is a process in which a liquid is dispensed onto a substrate. A template is brought into contact with the liquid and the liquid is cured. The cured liquid includes an imprint of any patterns formed in the template. In one embodiment, the imprint process is designed to imprint only a portion of the substrate. The remainder of the substrate is imprinted by moving the template to a different portion of the template and repeating the imprint lithography process.

Step and repeat imprint lithography processes

A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.

Design rule checking system and method

A first embodiment of the present invention pertains to a method of patterning a semiconductor device conductive feature while permitting easy removal of any residual masking layer which remains after completion of the etching process. A multi-layered masking structure is used which includes a layer of high-temperature organic-based masking material overlaid by either a patterned layer of inorganic masking material or by a layer of patterned high-temperature imageable organic masking material. The inorganic masking material is used to transfer a pattern to the high-temperature organic-based masking material and is then removed. The high-temperature organic-based masking material is used to transfer the pattern and then may be removed if desired. This method is also useful in the pattern etching of aluminum, even though aluminum can be etched at lower temperatures. A second embodiment of the present invention pertains to a specialized etch chemistry useful in the patterning of organic polymeric layers such as low k dielectrics, or other organic polymeric interfacial layers. This etch chemistry is useful for mask opening during the etch of a conductive layer or is useful in etching damascene structures where a metal fill layer is applied over the surface of a patterned organic-based dielectric layer. The etch chemistry provides for the use of etchant plasma species which minimize oxygen, fluorine, chlorine, and bromine content.

Method of etching patterned layers useful as masking during subsequent etching or for damascene structures

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

Provided is a method for forming fine pattern free from shear of pattern caused by charging and high in dry etch resistance by using a high molecular organic film containing an organometallic complex or a metallic salt in single-layer or multi-layer resist process and treating the surface of this film with a reducing agent to form a metallic layer on the surface.

Fine pattern forming method

A method of correcting design patterns in cells, having hierarchial structure and corresponding to exposure patterns, for proximity effects when exposing resist coated on a substrate to a charged-particle beam or to light. A first frame zone is provided having a predetermined width inside the boundary of each cell, and a second frame zone is provided having a predetermined width inside the first frame zone. Proximity effect correction operations are performed such that a pattern in the second frame zone and a pattern inside the second frame zone are used as a pattern to be corrected and a pattern in the first frame zone is used as a reference pattern when correcting pattern data in each cell for proximity effects and a pattern in the first frame zone in each cell is added to the pattern to be corrected and a pattern in the second frame zone in each cell is used as a reference pattern when correcting pattern data in a cell directly overlying each cell for proximity effect.

Method and apparatus for writing a pattern on a semiconductor sample based on a resist pattern corrected for proximity effects resulting from direct exposure of the sample by a charged-particle beam or light

Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.

Method of manufacturing isolated semiconductor devices

A method of manufacturing a semiconductor integrated circuit device of the bipolar type of the MOS type or an integration of the two types having high integration and high performance, in which the circuit includes a first device region of which the side surface and entire region of the lower portion of the active region are made of silicon oxide and a second device region of which the side surface and a part of the lower portion of the active region are made of silicon oxide. According to the present invention, a transistor whose bottom portion is opened and a transistor whose bottom portion is not opened can be freely provided on a substrate, thereby dividing the transistors into a transistor to which a voltage can be supplied from the substrate and a transistor to which the voltage can not be supplied from the substrate, so that the wiring which has been conventionally needed can be reduced. In addition, in such transistors which are completely separated, the parasitic effect with the circumference is completely prevented so that excellent characteristics can be provided.

Method of manufacturing a semiconductor integrated circuit device

PURPOSE: To shorten processing time by calculating proximity effect correction for each hierarchical layer and each cell while maintaining the hierarchical layer structure for design data having a hierarchical layer structure of cells. CONSTITUTION: If resist coated on a board is exposed, when proximity effect is supplemented for a design pattern having a hierarchical layer structure of cells, a first frame region having a predetermined width is provided inside the boundary of the cells, and a second frame region having a predetermined width is provided inside the first region. When pattern data in each cell is corrected for the proximity effect, the pattern in the second region and the pattern inside the second region are to be corrected, and the pattern in the first region is used as a reference pattern. When the pattern of a hierarchical layer cell directly above each cell is corrected for the proximity effect, the pattern in the first region in each cell is added as to be corrected, the pattern in the second region in each cell is used as a reference pattern, and proximity effect corrective operation is carried out. COPYRIGHT: (C)1991,JPO&Japio

Kenji Kawakita

Papers

Fine pattern forming method

Method and apparatus for writing a pattern on a semiconductor sample based on a resist pattern corrected for proximity effects resulting from direct exposure of the sample by a charged-particle beam or light

Method of manufacturing isolated semiconductor devices

Method of manufacturing a semiconductor integrated circuit device

Correcting method for proximity effect