A method of synthesizing integrated circuit (IC) design having DesignWare components comprising the steps of initially mapping DesignWare components, revising DesignWare component structure, ungrouping DesignWare components, and re-synthesizing DesignWare components. The step of initially mapping is performed using elaborate command and compile command of a logic synthesis tool. The step of ungrouping DesignWare components involves dissolving DesignWare modules to be merged with surrounding logic.

Method of handling macro components in circuit design synthesis

A method of efficiently characterizing modules of an integrated circuit (IC) design using a logic synthesis tool comprising the steps of defining a list of instances of the modules to characterize, and characterizing entire modules of said list of instances of the modules using a single invocation of characterize command of the logic synthesis tool.

Efficient top-down characterization method

The world-wide competitive economy is forcing us to utilize fully the best equipment and techniques available with efficient control of organizational structure to produce high quality, well-designed products at lower prices and in less time. Increasing awareness is being directed to the product design phase, because the more advanced CIM technologies are of little consequence unless the product design lends itself to the overall system utilizing all available and relevant technologies. For instance, the following statements represent the significance of product design.

Principles of concurrent engineering

This thesis provides a systematic approach to the system-level design of embedded signal processing applications. Such applications tend to have mixed hardware-software components and are often subject to severe cost, performance, and design-time constraints. Our approach is to codesign these systems. The code-sign approach allows the hardware and software designs to be tightly coupled throughout the design process. We focus on the four key problems of partitioning, cosynthesis, cosimulation, and design methodology management. Applications are assumed to be specified using synchronous dataflow semantics.
A key contribution of the thesis is to formulate the extended partitioning problem. In system-level design, applications are represented as task graphs where tasks (called nodes) have moderate to large granularity and each node has several implementation options differing in area and execution time. The extended partitioning problem involves the joint determination of the mapping (hardware or software), schedule, as well as the implementation option for each node, so that the overall area allocated to nodes in hardware in minimum. This problem is considerably harder (and richer) than the traditional binary partitioning that determines just the best mapping and schedule.
Both extended and binary partitioning problems are constrained optimization problems and are shown to be NP-hard. We first present an efficient heuristic, called GCLP, to solve the binary partitioning problem. The heuristic reduces the greediness associated with serial traversal-based algorithms by formulating a global criticality (GC) measure. The GC measure also permits an adaptive selection of the objective (optimizing either area or time). We then present an efficient heuristic for extended partitioning, called MIBS, that alternately uses GCLP and an implementation-bin selection procedure. The implementation-bin selection procedure chooses the bin that maximizes the area-reduction gradient. Solutions generated by both heuristics are shown to be reasonably close to optimal. Extended partitioning generates considerably smaller overall hardware area as compared to binary partitioning.
Our approach to cosynthesis is to generate synthesizeable descriptions of the hardware and software components and to use pre-existing synthesis tools such as Ptolemy and Hyper to generate the actual software and hardware implementations. Techniques for generating these synthesizeable descriptions, starting with a partitioned graph, are discussed. Cosimulation involves simulating the hardware, the processor, and the software that the processor executes, within a unified framework. The requirements of a cosimulation framework are discussed and the use of Ptolemy for hardware-software cosimulation is illustrated.
Due to the large system-level design space, the system-level design problem cannot, in general, be posed as a single well-defined optimization problem. Typically, the designer needs to explore the possible options, tools, and architectures. We believe that managing the design process plays an equally important role in system-level design, as do the tools used for different aspects of the design. To this end, we present a framework that supports design methodology management.
We embody all the above concepts in a tool called the Design Assistant. The Design Assistant contains tools for partitioning, synthesis, and simulation and operates in the design methodology management framework.

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System-level codesign of mixed hardware-software systems

An IP library management system includes IP data segregated into two separate databases: an IP database for storing virtual component data, and an IP catalog database for storing attributes pertaining to the stored virtual component data. The IP database and IP catalog database are connected over a local area network. An IP database file server acts as the intermediary between the IP database and the local area network, while one or more database servers act as the intermediary between the IP catalog database and the local area network. The local area network may be connected to a wide area network allowing remote access by a number of remote users. The IP library management system provides an IP authoring methodology and an IP integration methodology associated with the two databases. Users may access the IP library management system through a global computer network such as the Internet.

Intellectual property library management system

The MCC CAD Framework Methodology Management System (MMS) is used to describe and control distributed engineering activities in terms of design methodologies. The MMS provides a medium for tool and task description which includes extensible dependency semantics as well as access to data management, communication, and general computation services. The MMS architecture is resistant to network and host failures and provides mechanisms for efficient use of networked computing resources.

The MCC CAD framework methodology management system

The design of today's electronic systems involves the use of a growing number of complex CAD tools. Invoking and controlling these tools, independently or as part of a captured, multi-operation flow, remains an error-prone and largely unsolved problem. This problem is the focus of the Design Methodology Management Technical Subcommittee (DMMTSC) of the CAD Framework Initiative. This paper describes the DMM problem, establishes DMM requirements, and presents the state of the DMMTSC effort to define interface standards for proposed solutions.

Kenneth W. Fiduk

Papers

The MCC CAD framework methodology management system

Design methodology management-a CAD framework initiative perspective