Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18.

Semiconductor device and method for fabricating the same

In an active matrix display device, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shaped semiconductor region, is used as a switching element. Each of the TFT have offset regions and lightly doped drain (LDD) regions. Then, by supplying a selection signal to the gate lines, the TFTs are operated, thereby writing data to the pixel, while a suitable voltage is supplied to the capacitance line, a channel is formed thereunder and it becomes a capacitor. Thus the amount of discharge from the pixel electrode is reduced by the capacitor.

Active matrix display device

In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region of a first conductivity type, a gate trench which extends into the first semiconductor region, and a source trench which extends into the first semiconductor region. The source trench is laterally spaced from the gate trench.

Dual trench power MOSFET

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Superjunction Structures for Power Devices and Methods of Manufacture

A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Method for forming pitch independent contacts and a semiconductor device having the same

Self-aligned and/or isolated contacts are formed in a semiconductor device, while simultaneously providing device planarization. In one form, an imagable material is deposited directly on a substrate material. The imagable material is patterned to form a sacrifical plug on a portion of the substrate material. A substantially planar insulating layer is then deposited overlying the substrate material. The plug formed of the imagable material is then removed, thereby exposing a portion of the substrate material and defining a contact opening. A conductive layer is deposited and patterned to complete formation of a contact.

Process for forming a contact structure

Method for forming contact to a semiconductor device

A method requiring only a single mask results in an isolation oxide (50) which is the same size as, instead of becoming larger than, the dimension originally defined by the lithographic system. A buffer layer (14) is formed over the substrate (12). An oxidation resistant layer (16) is formed over the buffer layer (14). The oxidation resistant layer (16) is etched and a disposable sidewall spacer (30) is formed adjacent to the sidewall of the oxidation resistant layer (28), and a trench region is defined (36). The trench region (36) is etched to form a trench. The disposable sidewall spacer (30) is removed and a conformal layer (48) of oxidizable material is deposited over the trench sidewall (40) and the trench bottom surface (38). The conformal layer (48) is then oxidized to form electrical isolation in the isolation regions (26) of the substrate (12).

Kent J. Cooper

Papers

Method for forming pitch independent contacts and a semiconductor device having the same

Process for forming a contact structure

Method for forming contact to a semiconductor device

Method of forming recessed oxide isolation