Systems and methods for electromechanical oscillation monitoring are disclosed herein. In one embodiment, a method for monitoring electromechanical oscillation in a power system includes forming a power density spectrum in frequency domain based on phasor measurements collected from a plurality of locations in the power system and identifying an oscillation in the power density spectrum. The oscillation has a power density larger than other oscillations. The method also includes analyzing the identified oscillation in time domain to determine a damping characteristic of the identified oscillation and indicating that an insufficiently damped oscillation exists in the power system if the determined damping characteristic of the oscillation meets a predetermined condition.

Systems and methods for electromechanical oscillation monitoring

A modulated Class E transmitter is disclosed In one embodiment of the invention, the modulated Class E oscillator achieves high coil currents (˜1 A) and voltages (˜500V) with low power components by precisely timed injection of current when the oscillating current in the inductor passes through zero A detector circuit is used to trigger the current injection at the appropriate instant regardless of changes in the resonant frequency of the system Its phase can be adjusted to compensate for propagation delays in the drive circuitry, while amplitude modulation is accomplished by switching in additional reactive conductance to increase the current injected into the tank circuit Frequency modulation is accomplished in an alternate embodiment

Switched reactance modulated E-class oscillator design

A phase-locked loop (PLL) with reduced jitter is provided The PLL includes dual path voltage-controlled oscillator inputs, with a control voltage from a loop filter sent through a low gain path and an integrated error voltage sent through a high gain path The error voltage is derived from the difference between a reference value representing averaged control voltage and a predetermined portion of the control voltage

Phase locked loop with control voltage centering

A tuner (101) has a dual AGC function, and frequency-converts an input signal into an IF signal An orthogonal detector (102) calculates a complex signal from the IF signal A demodulator (103) demodulates a digital signal from the complex signals An error corrector (104) corrects the error of the digital signal A signal level detector (105) calculates a level judgment signal from the IF signal A demodulation level detector (107) detects a signal level of a demodulation signal on a desired band from an output signal of the demodulator When a demodulation level judgment unit (108) generates a judgment signal representing an influence from interference waves in adjacent channel affecting on a signal on the desired band from the demodulation signal, a control signal generator (106) feeds back a gain control signal to the tuner in accordance with the judgment signal

Digital broadcast receiver

Embodiments of the present invention may provide for independent setting of jitter tolerance and jitter transfer levels, and reduced jitter generation of a data transmission device, such as a clock and data recovery (CDR) circuit or the like. An architecture may provide for reconfigurability of a circuit for use in various applications. The architecture may include a multi-loop structure, such as a tri-loop structure.

Data cleaning with an asynchronous reference clock

A low phase noise third order phase lock loop which can track and eliminate microphonic disturbances and phase hits. The PLL utilizes a third order loop filter which incorporates two integrators. These two integrators, when coupled with the integration which occurs at the voltage control input of the voltage controlled oscillator within the PLL yield an open loop transfer function with a --18 dB/octave rolloff over a band of frequencies which at least encompasses the spectral content of the microphonic or phase hit phase noise disturbance to be eliminated. The open loop gain of the phase lock loop must be set high enough such that the phase lock loop does not oscillate and such that the loop converges and locks. The integrators are implemented with operational amplifiers with RC feedback networks. The values of the components in the RC feedback networks set the frequencies of two zeroes in the transfer function. The frequencies of these zeroes are set by proper selection of the R and C values to cause a change in slope of the open loop gain frequency response curve at the frequency of the zeroes from the -18 dB/octave rollof to a -6 dB/octave rolloff at the frequency of the zeroes. This causes the phase angle of the open loop PLL transfer function to be more positive than -180 degrees at the frequency at which the open loop gain magnitude frequency response curve falls to unity gain thereby achieving conditional stability. The open loop gain of the PLL is set such that the -18 dB/octave rolloff of the frequency response does not result in a gain of unity until a frequency is reached which is above the highest expected frequency deviation of the carrier caused by microphonic disturbances or phase hits. In the preferred embodiment, the gain is set high enough that the -18 dB/octave rolloff of the open loop gain frequency response extends over at least two decades and extends up to 10 kHz which encompasses substantially all the spectral content of the microphonic disturbance caused by package resonance which sources the phase noise to be eliminated.

Kent K. Johnson

Papers

Low phase noise oscillator frequency control apparatus and method