Kevin C. Kahn

TL;DR: In this article, a multi-processor programmable interrupt controller system is described, which includes an I/O interrupt controller for receiving interrupt requests from an IO subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for priority arbitration, using a standard message format and arbitration protocol.

TL;DR: In this article, the authors have outlined an ambitious vision which, in some respects, is a wide departure from present-day processors and platforms. But in reality, this vision is based on a continued evolution of Intel's drive for increased parallelism and our proven investment, research, development, manufacturing and unparalleled ecosystem enabling capability that, when taken together, will continue to lead us into an era of more powerful, versatile and efficient processing engines and platforms containing those engines.

TL;DR: In this paper, a data processor is described, which is capable of decoding and executing the first instruction of a first instruction set and the second instruction of an instruction set where both instructions originate from a single computer program.

TL;DR: In this paper, an address translator and a method for translating a linear address into a physical address for memory management in a computer is described, which can translate from a standard 32-bit linear address to a larger physical address with no increase in access time.

TL;DR: In this article, the authors propose an interface processor for providing an interface between peripheral subsystems and a generalized data processor, which enables data to be transferred between two address spaces by mapping a portion of the I/O address space into a part of the GDP address space.