A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A dual port video memory system includes a serial-to-parallel converter coupled to the input data port and a parallel-to-serial converter coupled to the output data port. Four-bit pixel values are clocked into the serial-to-parallel converter synchronous with an input clock signal and are provided by the parallel-to-serial converter synchronous with an output clock signal. The input and output clock signals may have different frequencies, but the negative-going edges of each of these clock signals are synchronized to the negative-going edges of a master clock signal.

Dual port video memory system having semi-synchronous data input and data output

A semiconductor memory for storing binary data which may be accessed more rapidly is disclosed which semiconductor memory includes a pair of differential bit lines for receiving signals corresponding to the binary data; a semiconductor memory device for storing binary data is coupled between the differential bit lines to provide signals corresponding to the binary data when reading the semiconductor memory device during the read cycle. A semiconductor clamping device is coupled between the differential bit lines to selectively provide a current path between the differential bit lines during the reading of the semiconductor device.

Differential bit line clamp

A self-timed RAM (2) having a two-phase read and write operating cycles which comprise a precharge phase and a discharge phase and which is clocked by a clock signal. The self-timed RAM comprises control means (18, 20, 24, 22, 26, 28, 30) for initiating and controlling the precharge phase followed by the discharge phase in response to a first transition of the clock signal. The self-timed RAM further comprises logic means (30, ERRFLG) which determines when either phase of the two-phase operating cycle has not been completed before the next first transition of the clock signal and in response thereto activates an error indicating means (ERRFLG) to indicate that an error may have occurred during the RAM operating cycle. A controlling system of the RAM can then determine that an error may have occurred during the RAM operating cycle by checking the error indicating means (ERRFLG).

Random access memories (RAM) and more particularly to self-timed RAMS

A method and apparatus for switching clocks comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal. The second circuit may be configured to generate a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal. The third circuit may be configured to select (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal.

Method and apparatus for switching clocks presented to synchronous SRAMs

Glitch lockout circuit for a static random access memory (RAM) which prevents the writing or reading of incorrect data when a system clock is switched from a standard clock source to an alternate clock source. A dummy bit line (60) is added to the memory arrangement which is always precharged during a first clock phase (PHI1) and discharged during a second clock phase (PHI2). The state of the dummy bit line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase. Thus, if the dummy bit line stays low, the second clock phase will stay low and none of the RAM cells will be accessed.

Kevin David Kolwicz

Papers

Glitch lockout circuit for memory array.