Showing papers by "Kewal K. Saluja published in 2015"

Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints

Abstract: As Integrated Circuits (ICs) become more complex through smaller semiconductor feature sizes and higher performance requirements, the thorough testing of silicon devices is becoming a greater economic challenge. System-on-Chip (SoC) test schedules not only need to achieve the shortest possible test application time, they must also satisfy new design constraints which are increasing test scheduling complexity, such as device power. Although many past studies of SoC test scheduling have addressed individual issues during test, none have present a model of test scheduling that has allowed for many different constraints to be enforced at once. By presenting a test scheduling formulation that allows the enforcement of many separate power and hardware constraints, including issues of test pins, as well as allowing the use of modern Dynamic Voltage and Frequency Scaling (DVFS) hardware to further compact test schedules, this study provides a generalized test scheduling formulation that will not only allow the enforcement of multiple testing constraints but will also allow for the further compaction of test schedules and reduction of test cost.

Transient Fault Resilient QR Factorization on GPUs

Abstract: With their inherent capability to exploit parallelism, GPUs have become a popular platform for data-intensive scientific computing applications. This trend is expected to continue as the number of computations required by scientific applications reach the petascale and even exascale range. As the minimum feature size of transistors decreases due to improving process technology, GPUs are becoming more vulnerable to transient faults caused by events such as power fluctuations and alpha particle strikes, therefore we need methods that guarantee correct computation even in the presence of such faults. In this paper, we develop and analyze three fault tolerant schemes, FC-O, PC-C and PC-CS, for the block Householder QR algorithm that can deal with faults in the streaming processor (SP) core of a GPU. We also present a transient fault injection mechanism for NVIDIA GPUs, which has the capability of injecting faults of varying durations. We show that two of our schemes, PC-C and PC-CS, have good error coverage and relatively low overhead, and can scale reasonably well at the petascale and exascale range.

Diagnosis of Delay Faults Considering Hazards

Abstract: It is very difficult, if not impossible, to design hazard free circuits in view of substantial delay uncertainties of gates and interconnects implemented in sub micron technologies. In this paper, we propose diagnosis methods for gate delay faults for such circuits. The fault simulation method employed by us uses eight values and calculates logic values as well as earliest transition times and latest transition times. It can deal with hazard signals more accurately than conventional methods. The proposed method uses a fault dictionary to deduce candidate faults which sufficiently explain the output responses of a circuit under diagnosis.

Thermal Extension of the Total Bandwidth Server

Abstract: A typical real-time application is composed of periodic tasks with hard deadline constraints. It must also service a periodic tasks that are generated in response to external and internal events. In addition to application's timing constraints, it is important that the system never violates thermal constraint due to its increasingly adverse impact on the processing platform. In this work, we propose a scheme for servicing a periodic tasks in thermally constrained hard real-time systems. We propose an algorithm, T2BS, which is a thermal extension of the Total Bandwidth Server [1]. We show that our algorithm is optimal in the sense that it meets periodic task timing constraints as well as system thermal constraints, and it supports the maximum rate of a periodic arrivals. Through extensive simulations we demonstrate the validity of theoretical results and perform the response time analysis of a periodic tasks.

Privacy Assurance in Data-Aggregation for Multiple MAX Transactions

Abstract: Mobile devices are now very popular in many applications, and there is a trend to use them in statistic surveys. The main technical issue is privacy assurance. In this paper, we propose a certification-based approach for privacy assurance in multiple transactions of a survey conducted by a third-party application (TPA), which wants to find the maximal values of private data of some member groups in a social society. In our proposal, the computation burden on an involved user to verify the privacy assurance does not increase with the number of users participating in the survey. Furthermore, similar to traditional surveys, the users only need to communicate with the TPA. These features distinguish our approach from the existing research in literature for secure multi-party computation.