To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.

Method for manufacturing SOI substrate

Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.

Compound semiconductor device and method of manufacturing the same

Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Semiconductor devices and methods of manufacturing the same

A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.

Nitride semiconductor device

In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer

PROBLEM TO BE SOLVED: To dissolve the generation insufficiency of a two-dimensional electron gas layer near a source electrode. SOLUTION: The thickness of a first non p-type layer 104 is non-uniform due to the formation of a projection (center part 103a). That is, since the pn junction interface of a p-type semiconductor crystal layer 103 and the first non p-type layer 104 is raised higher than the other part under a gate electrode G, the thickness of the first non p-type layer 104 is thinner than the other part under the gate electrode G. Also, the end of the thick film of the first non p-type layer 104 is extended so as to burrow right under the peripheral edge of a gate insulation film 106. Then, by the structure, the upper end face α of a depletion layer including a pn junction interface does not reach the interface of the first non p-type layer 104 and a second non p-type layer 105 near respective electrodes S and D for conduction. Also, the upper end face α of the depletion layer enters the inside of the second non p-type layer 105 under the gate electrode G. COPYRIGHT: (C)2007,JPO&INPIT

Field effect transistor

PROBLEM TO BE SOLVED: To provide a power supply circuit of a DC-DC converter capable of suppressing the magnitude of a recovery surge voltage being generated when a second semiconductor switching element is turned off without increasing the number of components. SOLUTION: A DC-DC converter comprises a first semiconductor switching element Q11 being connected in series between a DC power supply Vin and a load, a second semiconductor switching element Q12 for short-circuiting the load terminals by bypassing the DC power supply Vin and the first semiconductor switching element Q11, and a PWM control circuit alternately repeating a state for turning the second semiconductor switching element Q12 off by turning the first semiconductor switching element Q11 on and a state for turning the second semiconductor switching element Q12 on by turning the first semiconductor switching element Q11 off. Index in involution of the drain-source voltage proportional to the reciprocal of capacitance of the second semiconductor switching element Q12 when turned off is smaller than the index in involution of the drain-source voltage proportional to the reciprocal of capacitance of the first semiconductor switching element Q11 when turned off. COPYRIGHT: (C)2005,JPO&NCIPI

Power supply apparatus

PROBLEM TO BE SOLVED: To suppress generation of leakage current in an off-state. SOLUTION: A surface gate electrode 24 is formed on a single-crystal silicon layer 22 and a buried gate electrode 20 is formed under the single-crystal silicon layer 22. Namely, the buried gate electrode 20, the single-crystal silicon layer 22, and the surface gate electrode 24 are laid to overlap vertically. In such a structure, the extending direction of a depletion layer becomes the thickness direction of the single-crystal silicon layer 22. The thickness of the single-crystal layer 22 depends on the thin-film formation technology. Therefore, the single- crystal silicon layer 22 can be made to be 0.5 μm or less in thickness. Furthermore, generation of leakage current can be suppressed in an off-state.

Field-effect transistor having bidirectional current blocking function and its manufacturing method

PROBLEM TO BE SOLVED: To obtain a method of manufacturing a substrate with an SiC layer whose surface is less roughened. SOLUTION: This manufacturing method comprises a first process where a first substrate 9 composed of a silicon substrate 1 and an SiC layer 3 formed on the substrate 1 and a second substrate 15 composed of a second substrate 15 and a silicon oxide film 13 formed on the substrate 15 and pasted on each other interposing the SiC layer 3 between the silicon oxide film 13 and the silicon substrate 1 to form a third substrate 17 and a second process where the silicon substrate 1 is removed by wet-etching the third substrate 17 with (CH3)4NOH to make the SiC layer exposed.

Kigami Masahito

Papers

Field effect transistor

Power supply apparatus

Field-effect transistor having bidirectional current blocking function and its manufacturing method

MANUFACTURE OF SUBSTRATE WITH SiC LAYER