A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.

Method and apparatus for enhancing the performance of semiconductor memory devices

A sense amplifier control circuit for use in a semiconductor memory device is provided which comprises a sense amplifier comprising first transistors of a first conductivity type connected in the form of a latch type differential amplifier, a set driver corresponding to the sense amplifier and the set driver comprising a second transistor of a second conductivity type for connecting the common source line of the latch type differential amplifier to a restore power supply line.

Sense amplifier control circuit of semiconductor memory device

A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors. Corresponding wide and narrow lines are used for the second local sense amplifier drive transistors which couple the N channel transistors to ground. Each sense amplifier may be shared between first and second pairs of bit lines through the use of isolation transistors and a corresponding isolation signal.

Method of reading and writing data using local data read and local data write circuits

A cross-coupled sense amplifier includes a voltage-compensating balancing resistor serially connected between the drain of one of the P-channel transistors in the sense amplifier and the corresponding sensing/bit line node. The value of the balancing resistor is optimized so that the voltage imbalance between the P-channel transistor is minimized and sense amplifier sensitivity is maximized. A balancing resistor can also be placed in the N-channel transistors in the sense amplifier if desired. The balancing resistor in a typical application is about 100 to 200 ohms and fabricated from polysilicon.

Sense amplifier utilizing a balancing resistor

A distributed control circuit for a sense amplifier is provided in which each sense amplifier has a pair of sensing control transistors connected in serial with each sensing node of the sense amplifiers. Each gate of the sensing control transistors has a respective resistor connected in sequence from the gate of the uppermost sensing control transistor to the gate of the lowermost sensing transistor. A delay compensation resistor is connected by the unit of a sensing control transistor group having the number of the sensing control transistors as many as an integer k.

Distributed sensing control circuit for a sense amplifier of the memory device

The sensing control transistors are connected to sensing nodes of each sense amplifiers and are grouped by delay compensating metalic wires to reduce the noise caused by the peak current of the power line and to stabilize the operation of the sense amplifier. The powers (Vss,Vcc) are applied to the sensing nodes of the sense ampliers (SA1-SAn) through N and P-MOS sensing control transistors (N1-Nn, P1-Pn) and the sensing control signals are applied to the gates of the N and P-MOS sensing control transistors to make the operating time of each sense amplifiers be different. The sensing control transistors are grouped by K numbers and each transistor group is connected by the delay compensating resister (Rt).

Divided control circuit of sense amp for memory device

PURPOSE: To improve a sensing speed by connecting the gates of sensing control transistors successively via resistors in such a manner that sensing control signals are impressed thereon and varying the working times of the respective sense amplifiers from each other. CONSTITUTION: The sense amplifiers SA1 to SAn commonly connected to a 1/2 VCC precharging circuit PC are so connected that voltages VSS, VCC are respectively impressed on the sensing nodes S and S of the respective NMOS sense amplifiers and PMOS sense amplifiers of these amplifiers. The gates of the respective NMOS sensing control TRs N1 to Nn and PMOS sensing control TRs P1 to Pn are so connected that the sensing control signals-LA and LA are respectively impressed successively via the resistors R thereon. Then, the working times of the respective sense amplifiers SA1 to SAn vary from each other. As a result, the voltage noises in the voltages VSS, VCC of a power source line are decreased, the signal voltages of the bit lines are increased and the sensing speed is improved.

Sensing amplifier dividing controller of memory device

Verteilte lesesteuerschaltung fuer einen leseverstaerker einer speichereinrichtung

This circuit comprises: a) a plurality of detection monitoring transistors N1 to Nn making it possible to off-load the voltage on detection nodes, each of these detection monitoring transistors being connected to each of the corresponding detection nodes of a plurality of predetermined detection amplifiers SA1, SA2 ... SAn, these detection nodes being connected to a preload circuit PC; b) a plurality of detection monitoring transistors P1 to Pn making it possible to off-load the voltage on other detection nodes, each of these detection monitoring transistors being connected to each of the other corresponding detection nodes of the detection amplifiers, these other detection nodes together being connected to the preload circuit PC; and c) a plurality of resistive elements R each connected to the gate of one of the various detection monitoring transistors and mounted in series via each of these gates, so as to be able to sequentially delay the instants at which each of the other detection monitoring transistors is turned on following application of a detection monitoring signal to the gate of the first detection monitoring transistor, through the effect of the delay introduced by the resistive elements on the applied detection monitoring signal.

Kim Chang-Hyun

Papers

Distributed sensing control circuit for a sense amplifier of the memory device

Divided control circuit of sense amp for memory device

Sensing amplifier dividing controller of memory device

Verteilte lesesteuerschaltung fuer einen leseverstaerker einer speichereinrichtung

Distributed circuit for monitoring detection for memory component detection amplifier