A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Low density parity check decoder for regular LDPC codes

The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.

Method and apparatus for communications using turbo like codes

Various embodiments of the present invention provide systems and methods for mitigating latency in a data detector feedback loop. For example, a method for reducing latency in an error corrected data retrieval system is disclosed. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.

Systems and methods for mitigating latency in a data detector feedback loop

Methods, apparatuses, and systems are presented for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits, processing the outer encoded bits using an interleaver and a single parity check (SPC) module to produce intermediate bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, processing the inner encoded bits using a puncture module to produce punctured bits, and combining the data bits and the punctured bits to produce encoded outputs. Methods, apparatuses, and systems are also presented for performing data decoding based on soft channel metrics derived from a channel using various iterative techniques.

Method and apparatus for communications using improved turbo like codes

Various embodiments of the present invention provide systems and methods for variable iteration data processing.

Systems and methods for queue based data detection and decoding

A decoding device for decoding an input codeword bit stream using a generator polynomial represented by the product of a plurality of sub-polynomials disclosed. The decoding device comprises a plurality of serial concatenated decoders each having different generator polynomials, wherein a product of the different generator polynomials becomes said generator polynomial, the different generator polynomials are represented by the different sub-polynomials or by a product thereof, and a first-stage decoder out of the serial concatenated decoders receives said codeword bit stream. The decoders each perform soft decision, and the codeword is a linear block code.

Encoder/decoder with serial concatenated structure in communication system

PURPOSE: An encoder and a decoder having serial concatenated structure in a communication system are provided to reduce the size of trellis for a soft decision of lineal block encode, reduce the complexity of realization. CONSTITUTION: A component decoder(411) outputs decode word bit(kp) by performing MAP/SISO decoding with receiving information bit(kp) and redundancy bit(rp) corresponding to the uppermost step. A deinterleaver(412) outputs the decode word bit(kp) by deinterleaving. A component decoder(413) outputs decode word bit(k(p-1)) by performing MAP/SISO decoding with output decode word bit(n(p-1)) of the deinterleaver and receiving redundancy bit(r(p-1)). A deinterleaver(414) outputs the output decode word bit(k2) of front end component encoder by deinterleaving. A component decoder(415) outputs information bit(k1) as a result of final decode by performing MAP/SISO decoding with output encode word bit(n1) and redundancy bit(r1).

Kim Min-Goo

Papers

Encoder/decoder with serial concatenated structure in communication system

Encoder and decoder having serial concatenated structure in communication system

Decoder with serial concatenated structure in communication system

Dekodierer mit einer verketteten seriellen struktur in einem kommunikationssystem