A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal. The delay reduction unit is disposed between the input signal applying unit and the ground switch, and reduces a signal delay from when the clock signal to when the evaluation signal pair is output from the second output terminal pair.

Sense amplifier circuit and sense amplifier-based flip-flop having the same

A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic typically has one charging event per clock cycle and the charging event does not depend on the input signals. The differential feature masks the in-put value because a precharged output nodes is discharged during the evaluation phase. The dynamic feature breaks the input sequence: the discharged node is charged during the subsequent precharge phase.

Dynamic and differential cmos logic with signal-independent power consumption to withstand differential power analysis

A sampling circuit including a number of state elements or flip-flops The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input

Precision sampling circuit

A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal.

High-speed static xor circuit

The sense amplifier-based flip-flop circuit includes a pulse generator and a sense amplifier. The pulse generator is configured to generate a signal pulse in response to one of a first transition and a second transition of a clock signal. The sense amplifier is configured to sense differential input signals in response to the signal pulse and maintain the sensed differential input signals until a subsequent signal pulse is received.

Sense amplifier-based flip-flop circuit

Provided is a flip-flop capable of operating at high speed by reducing a clock-to-output delay The flip-flop includes a sense amplifier and a latch circuit The sense amplifier includes a first node and a second node, precharges the first node and the second node with a supply voltage according to a state of a clock signal, or receives and amplifies differential input signals according to the state of the clock signal, so as to output differential output signals to the first node and the second node The latch circuit is connected to the first node and the second node, and detects and latches the differential input signals according to the state of the clock signal and the differential output signals The flip-flop described above does not use a NAND gate, so that a clock-to-output delay can be reduced Therefore, the flip-flop has an advantage of operating at high speed

Kim Min-Su

Papers

Flip-flop for high-speed operation