A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly to (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are “stacked up” so that the orientation of the space transformer, hence the orientation of the tips of the probe elements, can be adjusted without changing the orientation of the probe card. Suitable mechanisms for adjusting the orientation of the space transformer, and for determining what adjustments to make, are disclosed. The interposer has resilient contact structures extending from both the top and bottom surfaces thereof, and ensures that electrical connections are maintained between the space transformer and the probe card throughout the space transformer's range of adjustment, by virtue of the interposer's inherent compliance. Multiple die sites on a semiconductor wafer are readily probed using the disclosed techniques, and the probe elements can be arranged to optimize probing of an entire wafer. Composite interconnection elements having a relatively soft core overcoated by a relatively hard shell, as the resilient contact structures are described.

Probe card assembly and kit, and methods of making same

A method is presented for forming a bumped substrate and for forming an electrical circuit which includes the bumped substrate. The method of forming the bumped substrate includes forming at least one electrically conductive polymer bump on each of a first set of bond pads of the substrate. At least one electrically conductive polymer bump is then formed on each of a second set of the bond pads of the substrate. The circuit is formed by selectively forming an organic protective layer around the bond pads of a second substrate by laser ablation of an organic protective coating on the second substrate. The electrically conductive polymer bumps on the first and second portions of the bond pads of the first substrate are then contacted with the bond pads of the second substrate, thereby forming the electrical circuit.

Method of forming electrically conductive polymer interconnects on electrical substrates

Interconnection elements (752) and/or tip structures (770) for interconnection elements (752) may first be fabricated upon sacrificial substrates (702) for subsequent mounting to electronic components (784) In this manner, the electronic components (784) are not 'at risk' during the fabrication process The sacrificial substrate (702) establishes a predetermined spatial relationship between the interconnection elements (752) which may be composite interconnection elements (752) having a relatively soft elongate element (752) as a core and a relatively hard (springy material) overcoat (754) Interconnection elements (752) may be fabricated upon tip structures (770), or may first be mounted to the electronic component (784) and the tip structures (770) joined to the free-ends of the interconnection elements (752) Tip structures (770) formed as cantilever beams are described

Fabricating interconnects and tips using sacrificial substrates

Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

Semiconductor device having leads for mounting to a surface of a printed circuit board

Flexible multilayer printed circuit boards are disclosed which utilize adhesiveless laminates interconnected in a generally superposed relationship by a conductive adhesive. In one embodiment, the adhesiveless laminates have relatively thin conductive layers and metallized through holes which exhibit high delamination resistance. The metallized through holes preferably have a thickness of at most about 25 microns, yet they are capable of withstanding multilayer assembly processes. High flexibility, reliability, packaging density, and environmental resistance are consequently available in a thin multilayer construction. In a further embodiment, adhesiveless dielectric layers are interposed between adhesiveless laminates to electrically insulate portions thereof. The adhesiveless dielectric layers may define relatively small apertures therein, thus providing greater packaging density for a multilayer printed circuit board.

Flexible multilayer printed circuit boards and methods of manufacture

A process for forming an integrated circuit pin grid array (268) comprising a flexible metal tape (20) and interconnect tape (18') adapted for use in tape automated bonding with a plurality of holes. Terminal pins (26a) are inserted into the holes and the tape and pins are disposed within a mold and firmly locked into the encapsulating resin (270). The heat sink (106) forms a portion of the exterior surface (272) of the package. The exterior base (247) of the heat sink is exposed to the external environment to facilitate heat removal. After the package (268) is removed from the mold a semiconductor chip (82) is attached to the interior base (245) of the heat sink by a die attach (272) and electrically connected to leads (21). A lid (276) seals the enclosure (278) using an adhesive or solder ring (280).

Process for manufacturing plastic pin grid arrays and the product produced thereby

A screenable dielectric (16) and a method for the manufacture of multi-layer circuits (10) by an additive process is provided. A plurality of conductive layers are separated by the screenable dielectric (16). During screen printing, vias (46) are formed in the dielectric (16) such that a selective portion of underlying circuit traces (14b) remains conductive. The screenable dielectric (16) has a high thixotropic index so that it readily flows through the screen and then rapidly increases in viscosity to minimize feature collapse. The conductive portions (14b) are electrically interconnected by a conductive paste (48) which may be deposited by screen printing or by direct writing.

Method and materials for forming multi-layer circuits by an additive process

A process for the assembly of a pin grid array electronic package by vacuum lamination is provided. A vacuum is applied to the package components at the same time the components are bonded with a dielectric sealant. The sealant flow into holes formed in the package base is improved thereby electrically isolating terminal pins which pass through the holes.

Assembly of electronic packages by vacuum lamination

A process plate for the manufacture of molded electronic packages such as plastic pin grid array packages is provided. The process plate is a single fixture which is used to position terminal pins, align the pins for electrical interconnection and form the base of the mold during encapsulation. In one embodiment, the process plate comprises a support plate which is used for all standard terminal pin configurations and a thin cover plate which is specific for each terminal pin configuration. The process plate reduces the number of fixtures required to mold an electronic package reducing both cost and assembly error.

Process plate for plastic pin grid array manufacturing

A process plate for the manufacture of molded electronic packages such as plastic pin grid array packages is provided. The process plate is a single fixture which is used to position terminal pins (24), align the pins (24) for electrical interconnection and form the base of the mold during encapsulation. In one embodiment, the process plate comprises a support plate (50) which is used for all standard terminal pin (24) configurations and a thin cover plate (60) which is specific for each terminal pin (24) configuration. The process plate reduces the number of fixtures required to mold an electronic package reducing both cost and assembly error.

Kin-Shiung Chang

Papers

Process for manufacturing plastic pin grid arrays and the product produced thereby

Method and materials for forming multi-layer circuits by an additive process

Assembly of electronic packages by vacuum lamination

Process plate for plastic pin grid array manufacturing

Process plate for plastic pin grid array and method of making