A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.

Short-channel Schottky-barrier MOSFET device and manufacturing method

Interface circuits for connecting gallium arsenide circuits with silicon circuits with the interface circuits using a mix of gallium arsenide and silicon devices. Preferred embodiments (200) connect gallium arsenide buffered FET logic circuits (202) with silicon CMOS circuits with a two branch interface circuit under CMOS supply voltages with a BFL logic branch (208-210) merged with a CMOS inverter branch (204-206).

Interface circuit operable to perform level shifting between a first type of device and a second type of device

A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.

Schottky barrier cmos device and method

The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate

Schottky barrier CMOS fabrication method

Electronic circuit containing at least one Schottky field effect transistor with contact elements having different Schottky barrier heights.

Kjell Bohlin

Papers

Integrated electron circuits having Schottky field effect transistors of P- and N-type