A method for providing an incentive for a viewer to watch and react to audio/video programming. The method includes prompting the viewer (54) during a television programming stream to provide an indicated response to an event within an indicated time period, detecting the indicated response (56) to the event, measuring a response time of the indicated response to the event, evaluating viewer performance based upon the response time, and providing the incentive to the viewer based upon the response time (60). The method involves a viewer actuating a pushbutton key (72) of a set-top box remote control unit and transmitting and recording the response via the set-top box. A media delivery device for providing incentives, rewards, discounts, marketing data (80), and measurements to a viewer and a media delivery network (78).

Method and system for managing timed responses to a/v events in television programming

A programmable power controller controls power between a primary power source and a secondary power source and powering first circuitry. The primary power source has a first voltage and the secondary power source has a second voltage. A control register has a first field, which is field used to activate circuitry used to direct power from the primary power source to the secondary power source. First logic circuitry compares the first voltage and the second voltage to determine which is greater and then couples the primary power source or the secondary power source, depending upon which is greater, to power the first logic circuitry, second logic circuitry, and memory. The memory is coupled to the first logic circuitry and is read and written to via an input/output buffer. The second logic circuitry is coupled to the memory and to said first logic circuitry and activates write protection circuitry to prevent writing to the memory if the secondary power source is powering the first logic circuitry, the second logic circuitry, and the memory.

Programmable power supply systems and methods providing a write protected memory having multiple interface capability

A method and apparatus for performing power on reset initialization in a data processing system (40). In one form, the present invention uses a circuit (71) to ensure that a node (65) always power up to the correct logic level. This node (65) can then be used to initialize a latch (83) so that the latch (83) always drives a predetermined logic level at its data output when the latch (83) powers up. The data output of latch (83) is a Power On Reset signal which is asserted during power on reset initialization and which is negated when power on reset initialization is completed.

Method and apparatus for performing power on reset initialization in a data processing system

A power-on reset circuit. The reset circuit provides an automatic reset pulse immediately after power-up. The supply voltage is provided to the reset circuit. An RC filter with a variable time constant provides a "hump" waveform which is coupled to a waveform shaper. The waveform shaper converts the hump voltage output from the RC filter into a reset signal. Latching mechanisms are included to prevent refiring of the reset signal.

CMOS power-on reset circuit

A power-on-reset signal is generated at a proper timing according to an object to which the power-on-reset signal is sent. A POR signal generating circuit for generating the power-on-reset signal is caused to operate with the voltage of an internal voltage generating circuit.

Power-on reset signal generator for semiconductor device

A power on reset pulse generating circuit, which comprises a flip-flop coupled through capacitors to an applied supply voltage to be resettable thereby, a time constant circuit including an array of diode connecting MOS transistors and a capacitor coupled to reset the flip-flop in response to a fast rise time of an applied supply voltage, and another MOS transistor connected to detect a level of a voltage at the output terminal to reset the flip-flop in response to a slow rise time of the applied supply voltage.

Power on reset pulse generating circuit sensitive to rise time of the power supply

PURPOSE:To obtain a stable power-on reset pulse independently of the rising speed of a power voltage by obtaining a power-on reset pulse initializing another circuit integrated on one and same chip from the output of a flip-flop at application of power supply or the output applied with waveform-shaping to the said output. CONSTITUTION:A flip-flop 10 set in response to the application of a power supply voltage and a power supply voltage detection circuit 20 detecting the rise of the power supply voltage over a prescribed potential to output a signal are provided, and a power-on reset pulse to initialize other circuit integrated on one and same chip is obtained from the output of the flip-flop 10 at the application of power supply or the output being the result of waveform-shaping the output of the flip-flop 10. That is, the power-on reset pulse circuit is set as soon as the power is applied and the pulse is generated from the output signal of the flip-flop reset by a signal being the result of retarding the output of the power supply voltage detection circuit 20. Thus, a stable power-on reset pulse is obtained independently of the rising speed of the power supply voltage.

Kobayashi Toshifumi

Papers

Power on reset pulse generating circuit sensitive to rise time of the power supply

Power-on reset pulse generating circuit